Difference between revisions of "CSC270 Lab 5 2011"
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* Energize the R and S inputs and transcribe the behavior of the flipflop in a timing diagram. | * Energize the R and S inputs and transcribe the behavior of the flipflop in a timing diagram. | ||
| − | * Build another RS flipflop | + | * Build another RS flipflop with NAND gates. |
* Similarly, draw the timing diagram that illustrates the behavior of the flipflop. | * Similarly, draw the timing diagram that illustrates the behavior of the flipflop. | ||
| Line 15: | Line 15: | ||
=Part 3= | =Part 3= | ||
| − | * Capture the behavior of the NAND RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. | + | * Capture the behavior of the NAND RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. Make sure you connect the GND of the board to the GND of the kit. |
| − | * Capture the behavior of the NOR RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. | + | * Capture the behavior of the NOR RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. Same comment about the GND signals. |
| − | * Edit the capture you | + | * Edit the capture you made (either draw it or edit the graphic file captured on your USB stick) and indicate which part of the timing diagram corresponds to the flipflop being |
| + | ** in "memory" state, | ||
| + | ** in "store 1" state, | ||
| + | ** in "store 0" state, and | ||
| + | ** in the "forbidden state." | ||
<br /> | <br /> | ||
Latest revision as of 12:56, 21 February 2011
--D. Thiebaut 15:59, 20 February 2011 (EST)
Part 1
- Build an RS flipflop with NOR gates, as in the previous lab.
- Energize the R and S inputs and transcribe the behavior of the flipflop in a timing diagram.
- Build another RS flipflop with NAND gates.
- Similarly, draw the timing diagram that illustrates the behavior of the flipflop.
Part 2
- Do the Tektronix Scope Lab
Part 3
- Capture the behavior of the NAND RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. Make sure you connect the GND of the board to the GND of the kit.
- Capture the behavior of the NOR RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board. Same comment about the GND signals.
- Edit the capture you made (either draw it or edit the graphic file captured on your USB stick) and indicate which part of the timing diagram corresponds to the flipflop being
- in "memory" state,
- in "store 1" state,
- in "store 0" state, and
- in the "forbidden state."
