Difference between revisions of "FPGA-Based Supercomputer"
(Created page with " ==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ FPGA Supercomputer ]<P>[where ], May 7, 2010== from [...") |
|||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | + | ==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ FPGA Supercomputer ]<P>[http://www.computerworlduk.com/ ComputerWorld UK], July 11, 2011== | |
| − | ==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ | ||
| − | FPGA Supercomputer ]<P>[ | ||
from [http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ computerworld UK]: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it. <br />It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds." | from [http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ computerworld UK]: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it. <br />It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds." | ||
Latest revision as of 22:35, 11 July 2011
FPGA Supercomputer ComputerWorld UK, July 11, 2011
from computerworld UK: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it.
It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds."
- Read more here...
