Xilinx ISE Lab No. 1: Schematics Input

--D. Thiebaut 16:53, 14 April 2012 (EDT)

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This lab is an introduction to Xilinx ISE and to the CoolRunner-II kit. Unfortunately the CoolRunner-II and its programming utility from Digilent works only with Windows XP, so we won't be able to download the design into the CPLD chip, but we can still energize and test the design with the ISE Simulator.
Note: You'll need a two-button mouse to work with the ISE. The Mac's magic mouse does not open up all the properties of the different commands.

Introduction

Xilinx's ISE is "Xilinx ISE[1] is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer."

The goal of this lab/tutorial is to get the reader familiar with the process of designing a simple digital electronic circuit, compiling it, and verifying it correct behavior with a simulator.

Knowledge of digital logic (basic gates, flip-flops, Moore machines) is assumed.

This lab is based on the excellent series of labs created for the CoolRunner CPLD by Tiffany Liu in her Independent Study in the CS. Dept. at Smith College.

Installation of Xilinx ISE 13.4 on Windows 7

The first step is to install the ISE. It is a long process that can take more than an hour, so be prepared and start early!

Refer to the updated installation instructions that can be found here.

Lab 1: Creating a 2-bit Adder with Schematics

New Project

• Open the ISE
• File/New Project
• Pick a name: TwoBitAdder
• Either accept the default location, or pick something like C:\Users\Smith\xilinx\
• Either accept the default working directory, or let it become what you just typed above.
• Top-Level source: Schematics

• Next

• Project Settings:
  • Family: CoolRunner2 CPLDs
  • Device: XC2C257 (this is the marking on the CPLD on the actual kit)
  • Package: TQ144 (also marked on the CPLD on the actual kit)
  • Speed: -7
  • Keep all others unchanged.

New Source

• Click on top left icon (see image to the right) to add a new source to the project.

• Pick Schematic as the type

• Name it with a name that makes sense, e.g. circuit1.

• If you need to remove gates, select the gate you want to delete, and click on the red cross icon in the top icon bar.

• Pick the Symbols tab (bottom of left pane)

• Select Logic in top list

• Select And2 and Xor2 gates and position them on sreen

• Add wires between the inputs of the two gates (two vertical wires in the shape of [ brackets)

• Add two horizontal writes between the wires just inserted and points that will become input tags.

• Add two input tags to the two input wires just addes, and two output tags to the two outputs of the gates.

• Right-click on the Tabs and rename the two input ones as A and B, and the two output ones as Carry and Sum.

• Type Control-S to save the schematics to file.

A Peek at Verilog

The ISE translates your schematics into Verilog and store it in this format so that it can process it when combined with other modules. You can take a peek at them and get a first glimpse at automatically generated verilog. It is not as "pretty" as what we will code by hand, but it gives an idea of the language and its syntax.

• Make sure your Design Window shows the Implementation files
• Click on the .sch file to select it.
• In the Process Window', open the Design Utilities menu and click on "View HDL Functional Model. That's the verilog equivalent of your schematics:

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 13.4
//  \   \         Application : sch2hdl
//  /   /         Filename : circuit1.vf
// /___/   /\     Timestamp : 04/16/2012 14:32:43
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: sch2hdl -intstyle ise -family xbr -verilog "Y:[...]/circuit1.vf" -w "Y:/Desktop/[...]/circuit1.sch"
//Design Name: circuit1
//Device: xbr
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module circuit1(A, 
                B, 
                Carry, 
                Sum);

    input A;
    input B;
   output Carry;
   output Sum;
   
   
   AND2  XLXI_1 (.I0(B), 
                .I1(A), 
                .O(Carry));
   XOR2  XLXI_2 (.I0(A), 
                .I1(B), 
                .O(Sum));
endmodule

• Then click on View HDL Instantiation Template. That's the code you'll use in other modules if you want these modules to use your 2-big adder:

// Verilog instantiation template [...]- Tue Apr 24 16:12:42 2012
//
// Notes: 
// To use this template to instantiate this component,cut-and-paste and then edit
//
// Instantiate the UUT
   circuit1 UUT (
		.Carry(    ), 
		.Sum(    ), 
		.B(    ), 
		.A(    )
   );

Implementation Constraints File

The purpose of the Implementation Constraints File (ICF) is to associate input and output tabs with actual pins of the CPLD chip we are using.

The image below shows all the pins available to us:

Note that we can use Pins 64, 66, 68, and 69 for LED outputs, and pins 39, 94, 124 and 143 for input pins.

• Click on the Design tab of the left window.

• Select the circuit1.sch file and right click on it.

• New Source. Pick Implementation Constraints File. Name it something like circuits as well. (It will get its own extension.)

• Check under the circuit1.sch menu item, there should now be a file called circuit1.ucf.

• Select the ucf file and in the lower pane (processes pane), open the User Constraints option and click on Edit Constraints.

• In the editor window on the right, enter the following lines:

NET A        LOC = P124; 
NET B        LOC = P38;

NET Carry    LOC = P68;
NET Sum      LOC = P69;

• Save with Control S

Implement Design

It is now time to

1. Synthesize
2. Translate
3. Fit the design to the chip, and
4. Generate the Programming File that can be downloaded to the device.

• Select the circuit1.sch file in the Hierarchy window
• In the Process window, double click on Implement Desgin. This will automatically call all the actions listed above. The result is a programming file that will appear in the TwoBitAdder project directory.

Downloading to the CPLD

• Unfortunately, we have to skip this step at this time as the CPLD Windows Utility that interfaces with the CPLD and allows downloading of programming file does not work under Windows 7. Only Windows XP is supported at this time (April 2012).

Testing the design with the simulator

This step will allow you to create a module that will make A and B take all the possible values ranging from 00, 01, 10, to 11, and see how the two-bit adder circuit reacts to it.

• First create a new simulation module: From the main menu, pick Project then New Source.

• Choose Verilog Test Fixture as the type of the module. Give it a meaningful name, for example test.

• Click Next and make sure that your original schematic module is selected.

• Next then Finish.

• the ISE will have generated a test module for us. It's almost what we need. We just need to modify it a tad, as shown below:

// Verilog test fixture created from schematic [...] - Mon Apr 16 14:48:13 2012

`timescale 1ns / 1ps

module circuit1_circuit1_sch_tb();

// Inputs
   reg B;
   reg A;

// Output
   wire Carry;
   wire Sum;

// Bidirs

// Instantiate the UUT
   circuit1 UUT (
		.Carry(Carry), 
		.Sum(Sum), 
		.B(B), 
		.A(A)
   );
	
// Initialize Inputs
   
      initial begin
		B = 0;
		A = 0;

		// wait 100 ns  
		#100;	
			 
		// after 10 ns, set B to 1
		#10 B = 1;
			 
		// after 10 ns, set A to 1, reset B to 0
		#10 A = 1;
		    B = 0;
			 
		// after 10 ns, set B to 1
		#10 B = 1;
		end
		
endmodule

• Click on the Simulation button on top of the Hierarchy pane.

• The ISim Simulator should appear in the Process pane, below.

• Double click on Behavioral Check Syntax

• Then, assuming the process completed successfully, double click on Simulate Behavioral Model

• A new window should open up, presenting a timing diagram. Use slider and the magnifying glass + and - icons to zoom in on the marker at Time 100ns, and see how Sum and Carry react to the changing A and B signals.

• Make sure you verify that the adder works correctly.

Challenge #1

• Use the same approach illustrated here and create a 3-bit adder.

Other Xilinx Tutorials

This lab is one of several tutorials on Xilinx and the CPLD-2. You may want to check this page for additional tutorials.