Difference between revisions of "CSC103: DT's Notes 1"
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To implement it with logic gates we make ''a'' and ''b'' inputs, and ''f'' the output of the circuit. Then ''b'' is fed into an inverter gate (NOT), and the output of the inverter into the input of an AND gate. The other input of the AND gate is connected to the ''a'' signal, and the output becomes ''f''. | To implement it with logic gates we make ''a'' and ''b'' inputs, and ''f'' the output of the circuit. Then ''b'' is fed into an inverter gate (NOT), and the output of the inverter into the input of an AND gate. The other input of the AND gate is connected to the ''a'' signal, and the output becomes ''f''. | ||
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| − | <center>[[Image:aANDNOTb.png | + | <center>[[Image:aANDNOTb.png]]</center> |
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| + | Given the equations for the sum and carry signals that we generated earlier, we can now compose them using logic gates as shown below: | ||
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| + | <center>[[Image:2BitAdderWithGates.png]]</center> | ||
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Revision as of 21:43, 16 September 2013
--© D. Thiebaut 08:10, 30 January 2012 (EST)
