Difference between revisions of "DT's Research Page"

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(Patents and Invention Disclosures)
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* [http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=/netahtml/PTO/search-bool.html&r=1&f=G&l=50&\
 
* [http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=/netahtml/PTO/search-bool.html&r=1&f=G&l=50&\
co1=AND&d=PTXT&s1=stefan-gheorghe.INNM.&OS=IN/stefan-gheorghe&RS=IN/stefan-gheorghe Associative Memory Device], Gheorgh\
+
co1=AND&d=PTXT&s1=stefan-gheorghe.INNM.&OS=IN/stefan-gheorghe&RS=IN/stefan-gheorghe] Associative Memory Device, Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu, '''United States Patent''' 7,069,386, granted June 27, 2006.
e Stefan, Dominique Thiebaut, Dan Tomescu, '''United States Patent''' 7,069,386, granted June 27, 2006.
 
 
* [http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1\
 
* [http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=/netahtml/srchnum.htm&r=1&f=G&l=50&s1\
=6,760,821.WKU.&OS=PN/6,760,821&RS=PN/6,760,821 Memory engine for the inspection and manipulation of data], Gheorghe St\
+
=6,760,821.WKU.&OS=PN/6,760,821&RS=PN/6,760,821 Memory engine for the inspection and manipulation of data], Gheorghe Stefan & Dominique Thiébaut, '''United States Patent''' 6,760,821, granted July 6, 2004 ([patent/USPatent6760821.htm cached]). Also issued as Patent #5227-0002WOKR (Korea).
efan & Dominique Thiébaut, '''United States Patent''' 6,760,821, granted July 6, 2004 ([patent/USPatent67608\
+
* A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a cache of fixed size, Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''', Sept. 1990
21.htm cached]). Also issued as Patent #5227-0002WOKR (Korea).
+
* A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, '''IBM Invention Disclosure''' YO889-0493, Jun. 1989.
* A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a c\
+
* A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''' YO889-0515, Jun. 1989.
ache of fixed size, Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''', Sept. 1990
 
* A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D\
 
. Thiébaut, '''IBM Invention Disclosure''' YO889-0493, Jun. 1989.
 
* A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, '''IBM I\
 
nvention Disclosure''' YO889-0515, Jun. 1989.
 
  
  

Revision as of 09:05, 8 July 2008

Dominique Thiébaut's Research Page



Industry

D. Thiébaut is one of the five co-founders of Gemicer, which after changing its name to [http://www.connextechnology.co\ m/index.asp Connex Technology], has now adopted the current name of BrightScale.

D. Thiébaut is the holder with George Stefan of two patents, one of which (US Patent 6,760,821) the company is based. \ Connex Technology/BrightScale is a fab-less start-up company conceived in April 2002, and funded by Adams Capital Manag\ ement (www.acm.com) in April 2003.

More information on the history of the Connex Engine can be found here.

Patents and Invention Disclosures

co1=AND&d=PTXT&s1=stefan-gheorghe.INNM.&OS=IN/stefan-gheorghe&RS=IN/stefan-gheorghe] Associative Memory Device, Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu, United States Patent 7,069,386, granted June 27, 2006.

=6,760,821.WKU.&OS=PN/6,760,821&RS=PN/6,760,821 Memory engine for the inspection and manipulation of data], Gheorghe Stefan & Dominique Thiébaut, United States Patent 6,760,821, granted July 6, 2004 ([patent/USPatent6760821.htm cached]). Also issued as Patent #5227-0002WOKR (Korea).

  • A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a cache of fixed size, Harold Stone, and D. Thiebaut, IBM Invention Disclosure, Sept. 1990
  • A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, IBM Invention Disclosure YO889-0493, Jun. 1989.
  • A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, IBM Invention Disclosure YO889-0515, Jun. 1989.



Selected Papers

Wikipedia

College, July 2007. [in French] ([http://cs.smith.e\ du/~thiebaut/wp Discussion blog])

Connex Memory/Connex Engine

  • [can07/Malita_stefan_thiebaut_can_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for E\

mbedded Computation], M. Malita, G. Stefan, D. Thiebaut, in ACM Sigarch Computer Architecture News, Vol. 35, No. 5,\

Dec. 2007.
  • [alps07/Malita_stefan_thiebaut_ALPS_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for\
Embedded Computation], G. Stefan, M. Malita, D. Thiebaut, in proceedings of ALPS, the 21st ACM International Con\

ference on Supercomputing, Seattle, WA, June 2007.

  • [barc07/thiebaut_malita_connex_pipeline.pdf Pipelining the Connex Array], D. Thiébaut, M. Malita, BARC07, Bost\

on, Jan. 2007.

  • [paper_iccgi06.pdf Local Alignment of DNA Sequences with the Connex Array], D. Thiébaut, G. Stefan, M. Malita,\
Int'l Conf. on Comp. in Global Information. Tech. (ICCGI06), Bucharest, Romania, Aug. 2006. (Awa\

rded best paper of ICCGI06).

  • [paper_anchor06.pdf Real-time Packet Filtering with the Connex Array], D. Thiébaut, M. Malita, Anchor/Isca06, \

Boston June 2006.

eacute;baut and G. Stefan, Tech Rep. 077, Dept. Computer Science, Smith College, Jan 2002. ([http://cs.smith.edu/~thieb\ aut/research/compression/paper.ps postscript])

gine], D. Thiébaut and G. Stefan, Tech Rep. 076, Dept. Computer Science, Smith College.





Connex Memory/Connex Engine

  • [can07/Malita_stefan_thiebaut_can_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for E\

mbedded Computation], M. Malita, G. Stefan, D. Thiebaut, in ACM Sigarch Computer Architecture News, Vol. 35, No. 5,\

Dec. 2007.
  • [alps07/Malita_stefan_thiebaut_ALPS_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for\
Embedded Computation], G. Stefan, M. Malita, D. Thiebaut, in proceedings of ALPS, the 21st ACM International Con\

ference on Supercomputing, Seattle, WA, June 2007.

  • [barc07/thiebaut_malita_connex_pipeline.pdf Pipelining the Connex Array], D. Thiébaut, M. Malita, BARC07, Bost\

on, Jan. 2007.

  • [paper_iccgi06.pdf Local Alignment of DNA Sequences with the Connex Array], D. Thiébaut, G. Stefan, M. Malita,\
Int'l Conf. on Comp. in Global Information. Tech. (ICCGI06), Bucharest, Romania, Aug. 2006. (Awa\

rded best paper of ICCGI06).

  • [paper_anchor06.pdf Real-time Packet Filtering with the Connex Array], D. Thiébaut, M. Malita, Anchor/Isca06, \

Boston June 2006.

eacute;baut and G. Stefan, Tech Rep. 077, Dept. Computer Science, Smith College, Jan 2002. ([http://cs.smith.edu/~thieb\ aut/research/compression/paper.ps postscript])

gine], D. Thiébaut and G. Stefan, Tech Rep. 076, Dept. Computer Science, Smith College,