Difference between revisions of "CSC270 Homework 4 Solution 2011"

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(Created page with "--~~~~ ---- <onlydft> =Extra Credit= <code><pre> # solution for Homework #4 ...")
 
 
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<onlydft>
 
<onlydft>
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=Problem #1=
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==Logic Diagrams==
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Here are some pictures from Tiffany's answers.
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<br />
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<br />
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[[Image:CSC270Hw4Prob1a.png]]
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<br />
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<br />
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[[Image:CSC270Hw4Prob1b.png]]
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<br />
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<br />
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One picture from Elizabeth's answer.  the "d=0" signal is connected to the most significant input congtrol bit.
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<br />
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<br />
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[[Image:CSC270Hw4Prob1c.png]]
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<br />
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<br />
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For the last diagram, the design is correct, but could have been simplified by setting the d input to 0 and leaving I8 to I15 unconnected (we use the symbol NC in diagrams to indicate the fact that an input or output is "not connected" to anything.
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==Code==
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<code><pre>
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# solution program for hw4                                                                                                                                     
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# D. Thiebaut                                                                                                                                                 
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#                                                                                                                                                             
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def mux4To1( I0, I1, I2, I3, C0, C1 ):
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    inputs = ( I0, I1, I2, I3 )
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    return inputs[ C0 + 2*C1 ]
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def decode3To8( I2, I1, I0 ):
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    outputs = [0, 0, 0, 0, 0, 0, 0, 0]
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    outputs[ I0 + I1*2 + I2*4 ] = 1
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    return outputs
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def main():
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    #--- verification of the majority voter ---                                                                                                               
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    print "Majority voter verification"
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    print "a b c | f "
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    print "------+---"
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    for a in [0,1]:
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        for b in [0,1]:
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            for c in [0,1]:
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                f = mux4To1( 0, c, c, 1, a, b )
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                print "%d %d %d | %d" % ( a, b, c, f )
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    #--- verification of decoder ---                                                                                                                           
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    print "\n\nDecoder verification"
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    print "a b c | I7 I6 I5 I4 I3 I2 I1 I0"
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    print "------+------------------------"
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    for a in [0,1]:
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        for b in [0,1]:
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            for c in [0,1]:
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                I7, I6, I5, I4, I3, I2, I1, I0 = decode3To8( a, b, c )
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                print "%d %d %d | %2d %2d %2d %2d %2d %2d %2d %2d" \
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                    % (a, b, c,  I7, I6, I5, I4, I3, I2, I1, I0 )
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main()
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</pre></code>
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==Output==
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<code><pre>
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Majority voter verification
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a b c | f
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------+---
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0 0 0 | 0
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0 0 1 | 0
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0 1 0 | 0
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0 1 1 | 1
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1 0 0 | 0
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1 0 1 | 1
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1 1 0 | 1
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1 1 1 | 1
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Decoder verification
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a b c | I7 I6 I5 I4 I3 I2 I1 I0
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------+------------------------
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0 0 0 |  1  0  0  0  0  0  0  0
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0 0 1 |  0  1  0  0  0  0  0  0
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0 1 0 |  0  0  1  0  0  0  0  0
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0 1 1 |  0  0  0  1  0  0  0  0
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1 0 0 |  0  0  0  0  1  0  0  0
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1 0 1 |  0  0  0  0  0  1  0  0
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1 1 0 |  0  0  0  0  0  0  1  0
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1 1 1 |  0  0  0  0  0  0  0  1
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</pre></code>
  
 
=Extra Credit=
 
=Extra Credit=
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</pre></code>
 
</pre></code>
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=RS Flip-Flops with NAND/NOR and XOR/XOR=
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* We cannot store both 1 or 0 in the NAND/NOR.
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* Similarly, we cannot store 1 or 0 in the XOR/XOR. 
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* Some of you used the kits to verify this.  VERY GOOD IDEA!
  
 
</onlydft>
 
</onlydft>

Latest revision as of 12:16, 1 March 2011

--D. Thiebaut 10:44, 1 March 2011 (EST)


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