Difference between revisions of "CSC103 Homework 2 Fall 2012"
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This homework is due on 10/4/12 at 9:00 a.m. | This homework is due on 10/4/12 at 9:00 a.m. | ||
| − | + | If you did the lab with a partner during the lab on Thursday, then you can submit one assignment with two names on it. Otherwise, please do the homework by yourself. | |
</bluebox> | </bluebox> | ||
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The truth table for such a circuit is shown below. the symbols a, b, and c represent input signals, while y is the output. | The truth table for such a circuit is shown below. the symbols a, b, and c represent input signals, while y is the output. | ||
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{| class="wikitable" | {| class="wikitable" | ||
| + | !colspan="3" | inputs | ||
| + | ! output | ||
| + | |- | ||
! a | ! a | ||
! b | ! b | ||
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| 0 | | 0 | ||
| 0 | | 0 | ||
| − | |0 | + | |<center>0</center> |
|- | |- | ||
| 0 | | 0 | ||
| 0 | | 0 | ||
| 1 | | 1 | ||
| − | |0 | + | | <center>0 </center> |
|- | |- | ||
| 0 | | 0 | ||
| 1 | | 1 | ||
| 0 | | 0 | ||
| − | |0 | + | |<center>0</center> |
|- | |- | ||
| 0 | | 0 | ||
| 1 | | 1 | ||
| 1 | | 1 | ||
| − | | 1 | + | | <center>1</center> |
|- | |- | ||
| 1 | | 1 | ||
| 0 | | 0 | ||
| 0 | | 0 | ||
| − | | 0 | + | | <center>0</center> |
|- | |- | ||
| 1 | | 1 | ||
| 0 | | 0 | ||
| 1 | | 1 | ||
| − | | 1 | + | | <center>1</center> |
|- | |- | ||
| 1 | | 1 | ||
| 1 | | 1 | ||
| 0 | | 0 | ||
| − | | 1 | + | | <center>1</center> |
|- | |- | ||
| 1 | | 1 | ||
| 1 | | 1 | ||
| 1 | | 1 | ||
| − | | 1 | + | |<center>1</center> |
|} | |} | ||
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;Question 1 | ;Question 1 | ||
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;Question 2 | ;Question 2 | ||
| − | :Convert your expression into a circuit containing logic gates. Draw it by hand (or with a computer drawing program, if you prefer). | + | :Convert your expression into a circuit containing logic gates. Draw it by hand (or with a computer drawing program, if you prefer). Yes, please draw it by hand on a piece of paper. Question 3 will ask you to transpose it into the simulator, but I want to see how you translate the logic expression into a series of gates connected by wires. I understand that it is a skill to draw esthetically pleasing schematics, so I put a page with examples of schematics to help you better organize your design. Pleaser refer to [[CSC103 Examples of Schematics with Logic Gates | this page for examples of schematics.]] |
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:Implement your circuit with the logic gate simulator we used in the lab on 9/27/12. Verify that your circuit behaves according to the truth table given above. | :Implement your circuit with the logic gate simulator we used in the lab on 9/27/12. Verify that your circuit behaves according to the truth table given above. | ||
| − | : Make a screen copy of your simulator window showing all the gates and the wiring, print it, and submit it with your homework. Below is an example of the type of image I | + | : Make a screen copy of your simulator window showing all the gates and the wiring, print it, and submit it with your homework. Below is an example of the type of image I would like you to submit: |
| − | + | <br /><br /> | |
<center> | <center> | ||
[[Image:ExampleOfGateSimulator.png|700px]] | [[Image:ExampleOfGateSimulator.png|700px]] | ||
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<br /> | <br /> | ||
| + | ==Reference== | ||
| + | You may find these links useful for figuring out how to capture the simulator window: | ||
| + | |||
| + | |||
| + | * http://windows.microsoft.com/en-US/windows-vista/Use-Snipping-Tool-to-capture-screen-shots | ||
| + | |||
| + | * http://www.themaclawyer.com/2006/11/mac-os-x/how-to-capture-all-or-part-of-your-screen/ | ||
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<br /> | <br /> | ||
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Latest revision as of 17:27, 3 October 2012
--D. Thiebaut 06:13, 27 September 2012 (EDT)
This homework is due on 10/4/12 at 9:00 a.m. If you did the lab with a partner during the lab on Thursday, then you can submit one assignment with two names on it. Otherwise, please do the homework by yourself.
Problem #1: A majority voter circuit
One circuit that is often found inside computing system is a majority voter. A majority voter is a circuit made of AND, OR and NOT gates that has 3 inputs and one output. The output is always the representation of the majority of the inputs. For example, if two or more of the inputs are 0, then the output is 0. If two or more of the inputs are 1, then the output is 1.
The truth table for such a circuit is shown below. the symbols a, b, and c represent input signals, while y is the output.
| inputs | output | ||
|---|---|---|---|
| a | b | c | y |
| 0 | 0 | 0 | |
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 0 | |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | |
| 1 | 1 | 1 | |
- Question 1
- What is the boolean expression for y? Express it as a follows:
y = ( (not a ) and ...
- and fill up the rest with not, and, or, a, b, and c.
- Question 2
- Convert your expression into a circuit containing logic gates. Draw it by hand (or with a computer drawing program, if you prefer). Yes, please draw it by hand on a piece of paper. Question 3 will ask you to transpose it into the simulator, but I want to see how you translate the logic expression into a series of gates connected by wires. I understand that it is a skill to draw esthetically pleasing schematics, so I put a page with examples of schematics to help you better organize your design. Pleaser refer to this page for examples of schematics.
- Question 3
- Implement your circuit with the logic gate simulator we used in the lab on 9/27/12. Verify that your circuit behaves according to the truth table given above.
- Make a screen copy of your simulator window showing all the gates and the wiring, print it, and submit it with your homework. Below is an example of the type of image I would like you to submit:
Reference
You may find these links useful for figuring out how to capture the simulator window:
