Difference between revisions of "CSC270 Class Page 2009"

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* [http://www.ti.com/sc/harris  Texas Instruments and Harris Semiconductors' Data Sheet Search Engine]
 
* [http://www.ti.com/sc/harris  Texas Instruments and Harris Semiconductors' Data Sheet Search Engine]
 
* [http://www.fairchildsemi.com/krkDir/krk.html Fairchild Semiconductors' Data Sheet Search Engine]
 
* [http://www.fairchildsemi.com/krkDir/krk.html Fairchild Semiconductors' Data Sheet Search Engine]
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* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/nte2114.pdf | 2114 1Kx4 RAM]
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== Motorola 68HC11==
 
== Motorola 68HC11==

Revision as of 10:56, 22 January 2009

Back to Main Page for CSC270


Prof

Dominique Thiébaut email
Dept. Computer Science
McConnell Hall, 208.
Telephone: 3854
Office hours MW 10:30-12:00, W 1-3, and by appointments

Weekly Schedule

Week Topics Reading
Week 1
1/26
  • TBA

 

Week 2
2/2
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Week 3
2/9
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Week 4
2/16
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Week 5
2/23
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Week 6
3/2
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Week 7
3/9
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Week 8
3/16

SPRING BREAK

 

Week 9
3/23
  •  

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Week 10
3/30
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Week 11
4/6
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Week 12
4/13
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Week 13
4/20
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Week 14
4/27
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Back To Main Page


Links and Resources

  • Pspice 9, Student version. An nice alternative to drawing schematics

by hand. Download.

Integrated Circuit Data-Sheets

Ic.gif

74LS01, 74LS02, 74LS03, 74LS04, 74LS05, 74LS08, 74LS09, 74LS10, 74LS12, 74LS13, 74LS15, 74LS20, 74LS21, 74LS22, 74LS26, 74LS27, 74LS28, 74LS30, 74LS32, 74LS33, 74LS37, 74LS38, 74LS40, 74LS42, 74LS47, 74LS48, 74LS51, 74LS54, 74LS55, 74LS74, 74LS75, 74LS76, 74LS83, 74LS85, 74LS86, 74LS90, 74LS95, 74LS138, 74HCT240, 74LS243, 74HCT244, 74LS259, 74HCT541

Motorola 68HC11

cryptic...

  • A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
    • Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
    • Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
    • The condition code register is covered in Section 3.5.

engineering description. of the 6811, its ports, and how it operates.

    • See Section 10 for a cycle-by-cycle description of the execution of each instruction.
    • See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.

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