Difference between revisions of "FPGA-Based Supercomputer"

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(Created page with " ==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ FPGA Supercomputer ]<P>[where ], May 7, 2010== from [...")
 
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==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/
 
==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/
FPGA Supercomputer ]<P>[where ], May 7, 2010==
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FPGA Supercomputer ]<P>[http://www.computerworlduk.com/ ComputerWorld UK], July 11, 2011==
  
 
from [http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ computerworld UK]: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it. <br />It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds."
 
from [http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/ computerworld UK]: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it. <br />It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds."

Revision as of 22:34, 11 July 2011

==[http://www.computerworlduk.com/news/it-business/3290494/jp-morgan-supercomputer-offers-risk-analysis-in-near-real-time/

FPGA Supercomputer ]

ComputerWorld UK, July 11, 2011== from computerworld UK: "Prior to the implementation, JP Morgan would take eight hours to do a complete risk run, and an hour to run a present value, on its entire book. If anything went wrong with the analysis, there was no time to re-run it.
It has now reduced that to about 238 seconds, with an FPGA time of 12 seconds."

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