* [http://www.xilinx.com/support/documentation/data_sheets/ds094.pdf CoolRunner2] data sheet and specs.
* [http://www.xilinx.com/support/documentation/data_sheets/ds094.pdf CoolRunner2] data sheet and specs.
+
* [http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ise_tutorial_ug695.pdf Xilinx Tutorial] on its ISE.
* <onlysmith>[http://cs.smith.edu/dftwiki/images/CPLDandVerilog.pdf Presentation PDF] on Xilinx's CoolRunner II CPLD and Synthesis and Testing of Schematics</onlysmith>
* <onlysmith>[http://cs.smith.edu/dftwiki/images/CPLDandVerilog.pdf Presentation PDF] on Xilinx's CoolRunner II CPLD and Synthesis and Testing of Schematics</onlysmith>
* [http://cs.smith.edu/classwiki/index.php/CSC270_Labs_--_CSC400-Circuit_Design_F2011 CSC270 Labs on the CoolRunner II], by Tiffany Liu, Smith College.
* [http://cs.smith.edu/classwiki/index.php/CSC270_Labs_--_CSC400-Circuit_Design_F2011 CSC270 Labs on the CoolRunner II], by Tiffany Liu, Smith College.
Answer of the day: It's a sequential circuit: it behaves differently depending on initial conditions!
It's a machine with 2 states: it has a state diagram!
We cannot use a truth table to represent its behavior
It has memory: it can store a bit
Why does it work? Because the two gates that form this circuit can be eith blocking or passing, and when they are passing, the state, whichever it is, is stable.
End of the lecture was with timing diagrams, and showing that Q and Q' can be in either one of the possible cases: 01 or 10, and we show that on the timing diagram.
Wednesday
Toward the D Flip-Flop:
From RS to RS with 1 input only
From RS with 1 input only to RS with a pulse clock latch signal
From RS with a latch signal to a Master/Slave (sorry, this is the way it is coined) flip-flop
Two examples: a two-state oscillator, and a controlled oscillator
Designing a FSM that has a command input. If the command signal (cmd) is 1, the FSM oscillates. If the command signal is 0, the FSM stays in its current state.
Draw the state diagram
Figure out the number of flip-flops needed
Draw the State table, associating States to values of the Q output(s)
Draw the State Transition table.
Define the D inputs as a function of the Q outputs
Draw the FSM with flip-flop(s) and combinational logic
Verify with a timing diagram that the circuit works
Wednesday
Review of multiplexers and decoders as simplifying design blocks
Sentence of the week, found in the 6811 Pocket Reference:
The term Big Endian comes from Jonathan Swift’s satire Gulliver’s Travels. In Swift’s book, a Big Endian refers to a person who cracks their egg on the big end. The Lilliputians considered the big endians as inferiors. The big endians fought a long and senseless war with the Lilliputians who insisted it was only proper to break an egg on the little end.
Negative (signed) numbers are covered in the 6811 Manual, In Section 3.
The Condition Code register is also covered in Section 3.
Week 11 4/09
Monday
Review of negative numbers.
New question: How can we extend a positive or negative number from 1 byte to two bytes?
Review Condition Code Register
Rule:
Every instruction that makes information pass through ALU will modify the CC bits (HINZVC). Typical instructions: Add, Sub, Shift, Rotate, Multiply, Divide, And, Or, Not, Xor, and Compare (which is a subtract operation).
Special instructions can modify individual bits: For example CLC and SEC can be used to clear or set the Carry bit.
Some instruction can have different outcome depending on some of the CC bits: Conditional Branches: BEQ, BNE, BLT, BGT.
The Compare (CMP) instruction:
It is a subtract operation that does not store the result of the subtraction, but instead sets the HINZVC bit depending on the result of the subtraction.
The Conditional Branch instructrions:
They operate as follows:
if specific CC bit == some predefined value:
PC = PC + displacement
else:
PC = PC + 1
For example:
BEQ, (Branch if equal)
if Z bit == 1:
PC = PC + displacement
else:
PC = PC + 1
Computing the displacement in hex. Case #1
LDAA alpha
CMPA #5 ; alpha==5?
BEQ same
diff: ... ; go here if != 5
...
...
same: ... ; go here if == 5
Assume BEQ is at Address 0010 and same at Address 0023. Address of diff label is at 0012 (because BEQ label takes 2 bytes). 0012 + displacement must be equal to 0023. Hence displacement is 11 (only 2 digits, as only 1-byte displacement allowed).
Case #2: branching back
same: ... ; go here if == 5
LDAA alpha
CMPA #5 ; alpha==5?
BEQ same
diff: ... ; go here if != 5
...
...
Assume BEQ is at address 0020, and same is at 0005. The displacement must be a negative number that, once added to 0022 (because that's the address of the instruction after BEQ), will result in 0005.
0022
+ XXXX
---------
0005
There are many different ways to compute XXXX. Which ever way we find, we find XXXX = FFE3, so the displacement is the lower byte, or E3.
Wednesday
Class Quiz:
Question 1: We know how to build an 8-bit adder with gates. How do we build an 8-bit subtracter?
Question 2: How can we build an 8-bit module that either adds or subtracts depending on a single command signal? If the signal is 0, the module adds two 8-bit values. If the signal is 1, the module subtracts one from the other.
Question of the day: Why couldn't you set the LED from the keyboard in the one before the last lab?
Adding RAM to the 6811. The 2114 1Kx4 static RAM chip. (image taken from www.doulos.com)
Observation: Interfacing 2114 to 6811 is almost pin-to-pin wiring. This is because 2114 designed to be compatible with most processors. This in turns forces manufacturer to design new hardware to be compatible with older parts ==> we are stuck in a generic type of architecture (which is based on von Neumann architecture at a higher-level).
