CSC270 Lab 5 2011

--D. Thiebaut 15:59, 20 February 2011 (EST)

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Part 1

• Build an RS flipflop with NOR gates, as in the previous lab.
• Energize the R and S inputs and transcribe the behavior of the flipflop in a timing diagram.

• Build another RS flipflop witn NAND gates.
• Similarly, draw the timing diagram that illustrates the behavior of the flipflop.

Part 2

• Do the Tektronix Scope Lab

Part 3

• Capture the behavior of the NAND RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board.

• Capture the behavior of the NOR RS flipflop when both R and S are connected to the Test-Point 1 and Test-Point 2 of the HP test board.

• Edit the capture you make and indicate which part of the timing diagram corresponds to the flipflop being in "memory" state, in "store 1" state, "store 0" state, and in the "forbidden state."