Xilinx ISE Four-Bit Adder in Verilog

--D. Thiebaut 11:03, 24 April 2012 (EDT)

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This lab should be done after the introduction lab on Verilog. It shows how to use two modules, one for the basic 3-bit full-adder (adding a to b with carry-in), and one that uses 4 of them to create a 4-bit adder with an output carry.

Full-Adder in Verilog

• The first task is start the Xilinx ISE and create a New Project. Let's call it FourBitAdder.
• Once the Project is created, add a New Source, of type Verilog Module. Call it MultiStages. It will contain 2 modules. The first one will be the 3-bit full adder.
• Define the ports as follows:
  • a, input
  • b, input
  • cin, input
  • s, output
  • cout, output
• Complete the code of the module so that it looks like this:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// MultiStages.v
//
//////////////////////////////////////////////////////////////////////////////////
module singleStage (
	 input a,
	 input b,
	 input cin,
	 output s,
	 output cout );
	 
	 assign s = a ^ b ^ cin;
	 assign cout = (a & b) | (a & cin) | (b & cin);
endmodule