CSC270 Homework 10 Solution 2012
--D. Thiebaut 14:50, 1 May 2012 (EDT)
Sketch of the Solution for Homework 10
Question 1
- Just write the code we derived in class. Notice that it has two loops, one for waiting for Ack to go low (or high, depending on parity), and one waiting for Ack to go high (or low).
- Make sure you add an extra jmp or bra instruction at the end to create a complete loop around the code, as we are interested in sending multiple bytes. I agree that this is an approximation, but try to be as close to the real thing as possible.
- When you add up the cycles you will find something like 42 cycles. At 1 μs a cycle, that 42 μs per byte. 1,000,000 μs / 42 = 23.8 KBytes. Not sure how some people found a transfer rate in the 200 KB/s range...
Question 2
- The hard part of this question was figuring out the number of states. The trick here is the fact that the FSM will clear the flip-flop that generates the go-ahead signal, and this clear signal must be transient. If that clear signal stays on for very long, the processor cannot preset the flipflop as the output will be blocked.
- We need at least 4 states
- One state where we wait for Q to be set by the processor when it sends a byte. Call it S0.
- From S0 we go to S1 were we activate Strobe and wait for Ack to change. Call it S1.
- From S1 we go to S2 when Ack changes. In S2 we reset Strobe and wait for Ack to change again.
- From S2 we go to S3 when Ack has gone back to its idle level. We can now activate the Clear signal to the outside flip-flop. But we do that quickly, and move on automatically to S0 where we'll wait for the processor to alert us again if another byte goes out. We do not want to reset the flipflop until we are fully done, because we don't want the processor to send another byte too soon. The sending of a new byte MUST be done once Ack has returned to its idle level.
- We get a simple cycle of states. If we were to implement something like this in real life we'd probably end up with more states depending on what the Ack signal starts at, and what Q starts at. Or we could decide to have a reset signal that resets everything in the correct position before anything is sent out. But for this homework it was fine to have just 4.
- Then you derive the circuit. I saw a lot of gates drawn on paper. It seems some of you forgot that decoders and multiplexers are great tools to reduce combinational circuits... :-o
- And for the choice of a clock, E is the only real signal around we can use. The great advantage of E is that it will make the setting of the different signals synchronous with the behavior of the processor, which is great.
Question 3
- Now that we have some hardware that takes care of the hand-shake, our software becomes simpler:
start: LDAA done ;4 the signal from the FSM
ANDA #1 ;2
BEQ start ;3 if signal not what we want, wait
LDAA 0,X ;4 get a char
STAA port ;4 send it out
INX ;3 increment pointer
JMP start ;3 wait before sending next char
;; total = 23 cycles
- We now have 23 cycles, which is roughly half the answer for the first question. So we are going to send roughly twice as many characters.
- You should always compare values that you get and comment on them. If you are asked what a quantity is in one case, and what it becomes in another case, even you are not asked, volunteer to comment on what it means. Here it means that you have added some hardware to your design and you are getting better performance. The hardware you added reduced the software in your program. Because you reduced your instruction count, you have the ability, assuming that your peripheral is very fast, to double your throughput: twice as many bytes sent as before.
- In computer architecture, this is one of the major lessons: the trade-off between hardware an software... Here you had an example of it.
