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Connex TechnologyBrightScalewww.acm.com More information on the history of the Connex Engine can be found here.

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Patents and Invention Disclosures

• Associative Memory Device, Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu, United States Patent 7,069,386, granted June 27, 2006.
• Memory engine for the inspection and manipulation of data, Gheorghe Stefan & Dominique Thiébaut, United States Patent 6,760,821, granted July 6, 2004 ([patent/USPatent6760821.htm cached]). Also issued as Patent #5227-0002WOKR (Korea).
• A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a cache of fixed size, Harold Stone, and D. Thiebaut, IBM Invention Disclosure, Sept. 1990
• A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, IBM Invention Disclosure YO889-0493, Jun. 1989.
• A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, IBM Invention Disclosure YO889-0515, Jun. 1989.

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Selected Papers

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Wikipedia

• What We Wiki, D. Thiebaut, Technical Report, Smith College, July 2007. [in French] (Discussion blog)

Connex Memory/Connex Engine

• [can07/Malita_stefan_thiebaut_can_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation], M. Malita, G. Stefan, D. Thiebaut, in ACM Sigarch Computer Architecture News, Vol. 35, No. 5, Dec. 2007.
• [alps07/Malita_stefan_thiebaut_ALPS_2007.pdf Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation], G. Stefan, M. Malita, D. Thiebaut, in proceedings of ALPS, the 21st ACM International Conference on Supercomputing, Seattle, WA, June 2007.
• [barc07/thiebaut_malita_connex_pipeline.pdf Pipelining the Connex Array], D. Thiébaut, M. Malita, BARC07, Boston, Jan. 2007.
• [paper_iccgi06.pdf Local Alignment of DNA Sequences with the Connex Array], D. Thiébaut, G. Stefan, M. Malita, Int'l Conf. on Comp. in Global Information. Tech. (ICCGI06), Bucharest, Romania, Aug. 2006. (Awarded best paper of ICCGI06).
• [paper_anchor06.pdf Real-time Packet Filtering with the Connex Array], D. Thiébaut, M. Malita, Anchor/Isca06, Boston June 2006.
• Ziv-Lempel Compression with the Connex Engine, D. Thiébaut and G. Stefan, Tech Rep. 077, Dept. Computer Science, Smith College, Jan 2002. (postscript)
• Local Alignments of DNA Sequences with the Connex Engine, D. Thiébaut and G. Stefan, Tech Rep. 076, Dept. Computer Science, Smith College, Jan 2002. (postscript).
• The Connex Engine: An In-Memory Device for Fast String Operations, G. Stefan, and D. Thiébaut, Tech. Rep. 074, Dept. Computer Science, Smith College, Nov. 2001. (postscript)
• Local Alignment of DNA Sequences with the Connex Engine, G. Stefan, and D. Thiébaut, Poster at WABI 2001, 1st Workshop on Algorithms in BioInformatios, BRICS, University of Aarhus, Denmark, August 2001.

Teaching Computer Science

• [ccsne07/teachingArchitecture.pdf On Startups and Teaching Computer Architecture], D. Thiébaut, CCSCNE 07, Rochester, NY, Apr. 2007.

Performance measuring tool

• [msr/msrpaper.pdf An MSR-based performance measuring tool for Intel Processors under Linux], E. Altieri, and D. Thiébaut, Tech. Rep. 075, Dept. Computer Science, Smith College, Dec. 2001.
  ([msr source code])

Parallel Programming with Transputers

• Parallel Programming in C for the Transputer, D. Thiébaut
• Randomized Routing for Message Passing Using Virtual Channels: Mitra, S, and D. Thiébaut, The Inebriated Router Algorithm, in proc. 1993 North American Transputer User Group Meeting Vancouver, B.C., Canada
  (source code)

Cache Memories and Coherence Protocols

• Footprints in the cache, D. Thiébaut and H. Stone, ACM Trans. on Comp. Syst.
• From the fractal dimension of the intermiss gaps to the cache miss-ratio, D. Thiébaut, IBM Journal of Research and Development
• On the fractal dimension of computer programs and its application to the computation of the cache miss-ratio, D. Thiébaut, IEEE Transactions on Computers
• Two economical directory schemes for large-scale cache coherent multiprocessors, Maa, Y. C., D. Pradhan, and D. Thiébaut, Computer Architecture News
• Improving disk cache performance with partitioning, Thiébaut, D., H. S. Stone, and J. L. Wolf, IEEE Transactions on Computers
• Synthetic traces for trace-driven simulation of cache memories, Theibaut, D., J. L. Wolf, and H. S. Stone, IEEE Trans. Computers
• A Model of workads and its ue in miss-rate prediction for fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, IEEE Transactions on Computers
• Modeling live and dead lines in cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, IEEE Transactions on Computers
• The hierarchical full-map directory scheme: Protocol and performance, Maa, Y. C., D. Pradhan, and D. Thiébaut, IEEE Transactions on Computers
• On the fractal dimension of computer programs and its application to the prediction of the cache miss ratio, D. Thiébaut, Computer Measurement Group Trans.
• Modeling of live lines and true sharing in multi-cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, in Proc. of the 1990 Int'l Conf. on Parallel Processing
• A hierarchical directory scheme for large-scale cache-coherent multiprocessors, Maa, Y. C., D. K. Pradhan, and D. Thiébaut, 1992 Int'l Parallel Processing Symposium

Chaos and nonlinear dynamics

• Smoothing Stange Attractors with Splines, Junheng Luo and D. Thiébaut, Tech. Rep. 045, Dept. Computer Science, Smith College. (postscript)

PGPerl

• WWW Access-Statistics with Pgperl, D. Thiébaut, Computers in Physics, Sept-Oct. 1996.