CSC270 Class Page 2009

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Revision as of 11:05, 22 January 2009 by Thiebaut (talk | contribs) (Integrated Circuit Data-Sheets)
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Prof

Dominique Thiébaut email
Dept. Computer Science
McConnell Hall, 208.
Telephone: 3854
Office hours MW 10:30-12:00, W 1-3, and by appointments

Weekly Schedule

Week Topics Reading
Week 1
1/26
  • TBA

 

Week 2
2/2
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Week 3
2/9
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Week 4
2/16
  • 2/16  
  • 2/18 Rally Day, No Class

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Week 5
2/23
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Week 6
3/2
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Week 7
3/9
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  • 3/11 Midterm Exam

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Week 8
3/16

SPRING BREAK

 

Week 9
3/23
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Week 10
3/30
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Week 11
4/6
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Week 12
4/13
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Week 13
4/20
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Week 14
4/27
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  • 4/29: 1-week Take-Home Final Exam

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Links and Resources

Software

  • Pspice 9, Student version. An nice alternative to drawing schematics by hand. Download.

Integrated Circuit Data-Sheets

Ic.gif

74LS22, 74LS26, 74LS27, 74LS28, 74LS30, 74LS32, 74LS33, 74LS37, 74LS38, 74LS40, 74LS42, 74LS47, 74LS48, 74LS51, 74LS54, 74LS55, 74LS74, 74LS75, 74LS76, 74LS83, 74LS85, 74LS86, 74LS90, 74LS95, 74LS138, 74HCT240, 74LS243, 74HCT244, 74LS259, 74HCT541

Motorola 68HC11 Documentation

  • Good source of info on the 6811.
  • 6811 FAQs.
  • The official Motorola | 68HC11A8 Data Sheet. Fairly cryptic...
  • A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
    • Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
    • Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
    • The condition code register is covered in Section 3.5.
  • M68HC11 Technical Reference, Motorola
    • Section 6.5 shows the instructions in logical groups.
  • M68HC11 Pocket Reference.
    • Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
  • 68HC11A8 Technical Reference: a hardware and engineering description. of the 6811, its ports, and how it operates.
    • See Section 10 for a cycle-by-cycle description of the execution of each instruction.
    • See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.





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