Difference between revisions of "CSC270 Class Page 2009"

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<center>
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[[Image:cant_sleep.png | 700px]]
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<br>From [http://xkcd.org/571/ xkcd]
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</center>
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=Prof and TA=
 
=Prof and TA=
 
{|
 
{|
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=Weekly Schedule=
 
=Weekly Schedule=
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<onlysmith>
 
{| style="width:100%" border="1"
 
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| Week 8 <br /> 3/16
 
| Week 8 <br /> 3/16
 
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'''SPRING BREAK'''
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<center>[[Image:dancingCalving.gif ]]</center>
 
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&nbsp;
 
&nbsp;
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| Week 9 <br /> 3/23
 
| Week 9 <br /> 3/23
 
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*The 6811 Processor: references
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[[Image:6811Motorola.jpg | 200px | right]]
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** The official Motorola [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11a8.pdf 68HC11A8 Data Sheet]. Fairly cryptic...
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−
** A Motorola [[Media:6811Manual.pdf | 6811 Manual]]. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
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* '''Monday:'''
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*** Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
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**The 6811 Processor: references
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*** Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
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*** The official Motorola [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11a8.pdf 68HC11A8 Data Sheet]. Fairly cryptic...
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*** The condition code register is covered in Section 3.5. Skip Section 4.  
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*** A Motorola [[Media:6811Manual.pdf | 6811 Manual]]. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
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** [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11ref-2002.pdf M68HC11 Technical Reference], from Motorola.
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**** Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
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***Section 6.5 shows the instructions in logical groups.
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**** Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
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* [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11pocket.pdf M68HC11 Pocket Reference].
+
**** The condition code register is covered in Section 3.5. Skip Section 4.  
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**Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
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*** [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11ref-2002.pdf M68HC11 Technical Reference], from Motorola.
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* [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11a8ref.pdf 68HC11A8 Technical Reference]: a hardware & engineering description. of the 6811, its ports, and how it operates.
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****Section 6.5 shows the instructions in logical groups.
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*** See Section 10 for a cycle-by-cycle description of the execution of each instruction.
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** [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11pocket.pdf M68HC11 Pocket Reference].
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*** See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.  
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***Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
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* [http://www.ele.uri.edu/Courses/ele205/6811-Instructions/index.html 6811 Instruction Set], with hexadecimal opcodes. A reverse map, from hex to instructions can be found [http://home.earthlink.net/~tdickens/68hc11/68hc11_opcode_map.html here.]  
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** [http://maven.smith.edu/~thiebaut/classes/270/6811/68hc11a8ref.pdf 68HC11A8 Technical Reference]: a hardware & engineering description. of the 6811, its ports, and how it operates.
 +
**** See Section 10 for a cycle-by-cycle description of the execution of each instruction.
 +
**** See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.  
 +
** [http://www.ele.uri.edu/Courses/ele205/6811-Instructions/index.html 6811 Instruction Set], with hexadecimal opcodes. A reverse map, from hex to instructions can be found [http://home.earthlink.net/~tdickens/68hc11/68hc11_opcode_map.html here.]  
 +
** [[Media:CSC270_Assembly_Instructions.pdf | 2-Page List]] of all the 6811 Instructions
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** [http://www.aspisys.com/asm11.htm Software] for the 6811
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*  '''Wednesday:'''
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** Concentration on Assembly Language
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** [[Image:CSC270_6811_Listing_Format.png | 200 px | right ]] Listing format
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*** opcodes,  mnemonics, directives, columnar format
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** The instructions
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** Addressing Modes: inherent, immediate, direct, extended, indexed, relative
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** Exercises, exercises, exercises!!!
 
----
 
----
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* [[CSC270_Lab_6 | Lab #6 ]]
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*&nbsp;
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* [[CSC270_Homework_7 | Homework #7]]
 
||
 
||
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*Read the [[Media:6811Manual.pdf |6811 Manual ]]
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*Read the [[Media:6811Manual.pdf |6811 Manual ]] for this week.  Quiz on Monday 3/30/09 on this material.
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*[[CSC270:_If_you_have_skipped_CSC231 | Crash course]] on Assembly Language
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*[http://maven.smith.edu/~thiebaut/classes/231_0708/crashcourse/  Crash course] on Assembly Language
  
  
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| Week 10 <br /> 3/30
 
| Week 10 <br /> 3/30
 
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||  
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* &nbsp;
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* '''Monday:'''
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** Quiz on the information in [[Media:6811Manual.pdf |6811 Manual ]] (You can skip Section 4)
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** Timing Diagrams: conventions (transitions, floating signals, unknown, propagation times)
 +
** The E and R/W' signals (see the Google book [http://books.google.com/books?id=TcxukvTzxBcC&pg=PA435&lpg=PA435&dq=6811+timing+read+write+clock&source=bl&ots=XwSUe1MtSY&sig=dAOl2Ktzk58xsVCz4i6ARogMNcY&hl=en&ei=LqbQScOpIaLrlQfA55HWCQ&sa=X&oi=book_result&resnum=4&ct=result#PPA218,M1 ''MC68HC11, an introduction''] by Han-Way Huang, Section 5.7)
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** The timing of the execution of a 6811 instruction
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** the E signal
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** the R/W' signal
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** Timing of complete instructions
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*** LDAA #3
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*** LDAA 03
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*** LDAA 0003
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*** LDAA 3,X
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*** STAA 03
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*** STAA 0003
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*** STAA 3,X
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** Timing of a full program
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* '''Wednesday'''
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** Exercise: timing of an endless loop (preparation for the lab)
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** The conditional branch instructions and relative addressing mode
 
----
 
----
 +
* [[CSC270_Lab_7 | Lab #7 ]]
 +
* [[CSC270_Homework_8 | Homework #8]]
  
−
* &nbsp;
 
 
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* &nbsp;
 
* &nbsp;
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| Week 11 <br /> 4/6
 
| Week 11 <br /> 4/6
 
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* &nbsp;
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*'''Monday'''
 +
** Relative Addressing
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** BRA, BEQ, BNE, etc.
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** Exercises
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* '''Wednesday'''
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** Designing a 1-bit I/O output port.
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** Decoding the address bus
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*** Ideal case: 1 RAM chip
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*** Case 2: 1 RAM + 1 ROM chips covering the whole space
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*** Case 3: 1 RAM + 1 ROM chips covering only 1/4 each of the whole address space
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*** Case 4: Add a memory-mapped 1-bit ouput port in the unused space
 
----
 
----
−
 
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* [[CSC270_Lab_8 | Lab #8 ]]
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*&nbsp;
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* [[CSC270_Homework_9 | Homework #9]] and [[CSC270_Homework_9_Solution | Solution]]
−
||  
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* &nbsp;
 
* &nbsp;
  
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| Week 12 <br /> 4/13
 
| Week 12 <br /> 4/13
 
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||  
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* &nbsp;
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[[Image:CSC270_74244.png | 100 px | right ]]
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[[Image:CSC270_74541.png | 100 px | right ]]
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[[Image:CSC270_74240.png | 100 px | right ]]
 +
 
 +
* '''Monday''':
 +
** [[CSC270_Lab_8_1/2 | Mini Lab]]: Two-bit port ( from [[CSC270_Lab_8#Two-bit_Port | Lab #8]])
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** Generating [http://www.electronics-project-design.com/Infrared-remote-control-software.html signals] for a remotely controlled device
 +
* '''Wednesday'''
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** Tri-state drivers
 +
 
 
----
 
----
−
 
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* [[CSC270_Lab_9 | Lab #9]]
−
* &nbsp;
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* [[CSC270_Homework_10 | Homework #10 ]] and [[CSC270_Homework_10_Solution | Solution]]
 
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* &nbsp;
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* Read the section on Tri-state buffers in Mano's textbook 
  
 
<!-- ================================================================== -->
 
<!-- ================================================================== -->
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| Week 13 <br /> 4/20
 
| Week 13 <br /> 4/20
 
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||  
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* &nbsp;
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[[Image:CSC270_centronics.jpg | 150px | right ]]
 +
[[Image:CSC270_parallelPortTiming.jpg | 150px | right]]
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* '''Monday''': The Parallel Port.  Control, Status, Data registers.
 +
** Signals (see [http://www.nullmodem.com/Centronics.htm this link])
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** Protocol with Strobe and Ack (see [[Media:CSC270_ParallelPort.pdf | this document]])
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** Driver code for outputting a byte to a Centronics Port
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* '''Wednesday''': the 2114 RAM
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** Timing requirement of the 2114
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** Wiring a 2114 to a 6811
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** Software testing
 
----
 
----
−
 
+
* [[CSC270_Lab_10 | Lab #10]]
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*&nbsp;
+
* [[CSC270_Homework_11 | Homework #11 ]] &nbsp;  
 
||  
 
||  
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* &nbsp;
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* Parallel Port References
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** [http://www.nullmodem.com/Centronics.htm Signal] description
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**  [[Media:CSC270_ParallelPort.pdf | Protocol ]]
 +
** [[Media:CSC270_75574.pdf | Octal D-Flipflop]]
 
<!-- ================================================================== -->
 
<!-- ================================================================== -->
 
|- style="background:#eeeeff" valign="top"
 
|- style="background:#eeeeff" valign="top"
 
| Week 14 <br /> 4/27
 
| Week 14 <br /> 4/27
 
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||  
−
* &nbsp;
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[[Image:Sim2.jpg | right | 150 px]]
−
* 4/29: <font color="purple">'''1-week Take-Home Final Exam'''</font>
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* '''Monday''': Selected Topics in Computer Architecture
 +
** [[CSC270 Exercises on Memory Configuration | Exercises]] on memory
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** ROM-based sequencers
 +
** Hardware simulator
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<!--A bird's eye view of Computer Architecture. 
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** Processors: microprogram, caches, pipeline, Branch-Prediction Table
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** Ports: USB
 +
** Memory: dynamic RAM-->
 +
* '''Wednesday''':  
 +
* <font color="purple">'''1-week Take-Home Final Exam'''</font>
 +
* No lab
 
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* &nbsp;
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* [[CSC270 Final Exam | Final Exam]]
 
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* &nbsp;
 
* &nbsp;
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|}
 
|}
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</onlysmith>
 
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[[CSC270 | Back]] To Main Page
+
[[CSC270 2009 | Back]] To Main Page
 
----
 
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==Integrated Circuit Data-Sheets==
 
==Integrated Circuit Data-Sheets==
−
  [[Image:Ic.jpg | right]]
+
  [[Image:Ic.jpg |250px | right]]
  
 
* [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/xor.html Java Applets] demonstrating most logical gates
 
* [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/xor.html Java Applets] demonstrating most logical gates
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* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/DM9368.pdf  9368]
 
* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/DM9368.pdf  9368]
−
* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/nte2114.pdf  2114 1Kx4 RAM]
+
* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/nte2114.pdf  2114 1Kx4 RAM] ([[Media:2114_datasheet.pdf | with  timing information]] )
 +
* [[Media:CSC270_75574.pdf | Octal D-Flipflop]] (we do not have these chips in our current collection of chips)
  
 
== Motorola 68HC11 Documentation==
 
== Motorola 68HC11 Documentation==
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<br />
 
<br />
 
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<br />
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[[CSC270 | Back]] To Main Page
 
[[CSC270 | Back]] To Main Page
 
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<br /><br />
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[[Category:CSC270]]

Latest revision as of 08:47, 7 October 2010

Back to Main Page for CSC270

Cant sleep.png
From xkcd

Prof and TA

Dominique Thiébaut email
Dept. Computer Science
McConnell Hall, 208.
Telephone: 3854
Office hours MW 10:30-12:00, W 1-3, and by appointments


The TA for the class is Lei Lei, and her hours and location are available here

Weekly Schedule


This section is only visible to computers located at Smith College

Back To Main Page

Links and Resources

Programs

Software

Pspice9.jpg

PSpice 9

  • Pspice 9, Student version. An nice alternative to drawing schematics by hand.
  • This is a Windows version. (I have tried to make it work under wine/Mac OS X but haven't been able to make it load the libraries correctly)
  • Make sure you select the schematics option when installing the software.
  • Select Tools/Schematics when starting the editor
  • The schematics editor is located in C:\Program Files\OrCAD_Demo\PSpice\PDesign.exe upon installation.
  • Download here!
  • PSpice Tutorial

Integrated Circuit Data-Sheets

Ic.jpg

Motorola 68HC11 Documentation

6811.jpg
  • Good source of info on the 6811.
  • 6811 FAQs.
  • The official Motorola | 68HC11A8 Data Sheet. Fairly cryptic...
  • A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
    • Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
    • Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
    • The condition code register is covered in Section 3.5.
  • M68HC11 Technical Reference, Motorola
    • Section 6.5 shows the instructions in logical groups.
  • M68HC11 Pocket Reference.
    • Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
  • 68HC11A8 Technical Reference: a hardware and engineering description. of the 6811, its ports, and how it operates.
    • See Section 10 for a cycle-by-cycle description of the execution of each instruction.
    • See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.




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