Difference between revisions of "CSC270 Class Page 2009"
(→Weekly Schedule) |
(→Motorola 68HC11 Documentation) |
||
| (25 intermediate revisions by the same user not shown) | |||
| Line 2: | Line 2: | ||
---- | ---- | ||
__TOC__ | __TOC__ | ||
| + | |||
| + | <center> | ||
| + | [[Image:cant_sleep.png | 700px]] | ||
| + | <br>From [http://xkcd.org/571/ xkcd] | ||
| + | </center> | ||
| + | |||
=Prof and TA= | =Prof and TA= | ||
{| | {| | ||
| Line 16: | Line 22: | ||
=Weekly Schedule= | =Weekly Schedule= | ||
| − | + | <onlysmith> | |
{| style="width:100%" border="1" | {| style="width:100%" border="1" | ||
|- style="background:#ffdead;" | |- style="background:#ffdead;" | ||
| Line 283: | Line 289: | ||
---- | ---- | ||
* [[CSC270_Lab_8 | Lab #8 ]] | * [[CSC270_Lab_8 | Lab #8 ]] | ||
| − | * [[CSC270_Homework_9 | Homework #9]] | + | * [[CSC270_Homework_9 | Homework #9]] and [[CSC270_Homework_9_Solution | Solution]] |
|| | || | ||
* | * | ||
| Line 304: | Line 310: | ||
---- | ---- | ||
* [[CSC270_Lab_9 | Lab #9]] | * [[CSC270_Lab_9 | Lab #9]] | ||
| − | * [[CSC270_Homework_10 | Homework #10 ]] | + | * [[CSC270_Homework_10 | Homework #10 ]] and [[CSC270_Homework_10_Solution | Solution]] |
|| | || | ||
* Read the section on Tri-state buffers in Mano's textbook | * Read the section on Tri-state buffers in Mano's textbook | ||
| Line 312: | Line 318: | ||
| Week 13 <br /> 4/20 | | Week 13 <br /> 4/20 | ||
|| | || | ||
| + | [[Image:CSC270_centronics.jpg | 150px | right ]] | ||
| + | [[Image:CSC270_parallelPortTiming.jpg | 150px | right]] | ||
* '''Monday''': The Parallel Port. Control, Status, Data registers. | * '''Monday''': The Parallel Port. Control, Status, Data registers. | ||
| − | ** Signals (see [http:// | + | ** Signals (see [http://www.nullmodem.com/Centronics.htm this link]) |
** Protocol with Strobe and Ack (see [[Media:CSC270_ParallelPort.pdf | this document]]) | ** Protocol with Strobe and Ack (see [[Media:CSC270_ParallelPort.pdf | this document]]) | ||
| − | * | + | ** Driver code for outputting a byte to a Centronics Port |
| + | * '''Wednesday''': the 2114 RAM | ||
| + | ** Timing requirement of the 2114 | ||
| + | ** Wiring a 2114 to a 6811 | ||
| + | ** Software testing | ||
---- | ---- | ||
| − | + | * [[CSC270_Lab_10 | Lab #10]] | |
| − | * | + | * [[CSC270_Homework_11 | Homework #11 ]] |
|| | || | ||
* Parallel Port References | * Parallel Port References | ||
| − | ** | + | ** [http://www.nullmodem.com/Centronics.htm Signal] description |
| − | ** Protocol | + | ** [[Media:CSC270_ParallelPort.pdf | Protocol ]] |
| + | ** [[Media:CSC270_75574.pdf | Octal D-Flipflop]] | ||
<!-- ================================================================== --> | <!-- ================================================================== --> | ||
|- style="background:#eeeeff" valign="top" | |- style="background:#eeeeff" valign="top" | ||
| Week 14 <br /> 4/27 | | Week 14 <br /> 4/27 | ||
|| | || | ||
| − | * | + | [[Image:Sim2.jpg | right | 150 px]] |
| − | * | + | * '''Monday''': Selected Topics in Computer Architecture |
| + | ** [[CSC270 Exercises on Memory Configuration | Exercises]] on memory | ||
| + | ** ROM-based sequencers | ||
| + | ** Hardware simulator | ||
| + | <!--A bird's eye view of Computer Architecture. | ||
| + | ** Processors: microprogram, caches, pipeline, Branch-Prediction Table | ||
| + | ** Ports: USB | ||
| + | ** Memory: dynamic RAM--> | ||
| + | * '''Wednesday''': | ||
| + | * <font color="purple">'''1-week Take-Home Final Exam'''</font> | ||
| + | * No lab | ||
---- | ---- | ||
| − | * | + | * [[CSC270 Final Exam | Final Exam]] |
|| | || | ||
* | * | ||
| Line 337: | Line 360: | ||
|} | |} | ||
| − | + | </onlysmith> | |
---- | ---- | ||
| − | [[CSC270 | Back]] To Main Page | + | [[CSC270 2009 | Back]] To Main Page |
---- | ---- | ||
| Line 359: | Line 382: | ||
==Integrated Circuit Data-Sheets== | ==Integrated Circuit Data-Sheets== | ||
| − | [[Image:Ic.jpg | right]] | + | [[Image:Ic.jpg |250px | right]] |
* [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/xor.html Java Applets] demonstrating most logical gates | * [http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/xor.html Java Applets] demonstrating most logical gates | ||
| Line 367: | Line 390: | ||
* [http://cs.smith.edu/~thiebaut/classes/270/datasheets/DM9368.pdf 9368] | * [http://cs.smith.edu/~thiebaut/classes/270/datasheets/DM9368.pdf 9368] | ||
| − | * [http://cs.smith.edu/~thiebaut/classes/270/datasheets/nte2114.pdf 2114 1Kx4 RAM] | + | * [http://cs.smith.edu/~thiebaut/classes/270/datasheets/nte2114.pdf 2114 1Kx4 RAM] ([[Media:2114_datasheet.pdf | with timing information]] ) |
| + | * [[Media:CSC270_75574.pdf | Octal D-Flipflop]] (we do not have these chips in our current collection of chips) | ||
== Motorola 68HC11 Documentation== | == Motorola 68HC11 Documentation== | ||
| Line 389: | Line 413: | ||
<br /> | <br /> | ||
<br /> | <br /> | ||
| + | |||
---- | ---- | ||
[[CSC270 | Back]] To Main Page | [[CSC270 | Back]] To Main Page | ||
---- | ---- | ||
| + | <br /><br /> | ||
| + | [[Category:CSC270]] | ||
Latest revision as of 08:47, 7 October 2010
Back to Main Page for CSC270
Contents
From xkcd
Prof and TA
|
Dominique Thiébaut email |
The TA for the class is Lei Lei, and her hours and location are available here
Weekly Schedule
Back To Main Page
Links and Resources
Programs
- A Python program that generates a truth table.
Software
PSpice 9
- Pspice 9, Student version. An nice alternative to drawing schematics by hand.
- This is a Windows version. (I have tried to make it work under wine/Mac OS X but haven't been able to make it load the libraries correctly)
- Make sure you select the schematics option when installing the software.
- Select Tools/Schematics when starting the editor
- The schematics editor is located in C:\Program Files\OrCAD_Demo\PSpice\PDesign.exe upon installation.
- Download here!
- PSpice Tutorial
Integrated Circuit Data-Sheets
- Java Applets demonstrating most logical gates
- Texas Instruments and Harris Semiconductors' Data Sheet Search Engine
- Fairchild Semiconductors' Data Sheet Search Engine
- 74LS00, 74LS01, 74LS02, 74LS03, 74LS04, 74LS05, 74LS08, 74LS09, 74LS10, 74LS12, 74LS13, 74LS15, 74LS20, 74LS21, 74LS22, 74LS26, 74LS27, 74LS28, 74LS30, 74LS32, 74LS33, 74LS37, 74LS38, 74LS40, 74LS42, 74LS47, 74LS48, 74LS51, 74LS54, 74LS55, 74LS74, 74LS75, 74LS76, 74LS83, 74LS85, 74LS86, 74LS90, 74LS95, 74LS138, 74HCT240, 74LS243, 74HCT244, 74LS259, 74HCT541
- 9368
- 2114 1Kx4 RAM ( with timing information )
- Octal D-Flipflop (we do not have these chips in our current collection of chips)
Motorola 68HC11 Documentation
- Good source of info on the 6811.
- 6811 FAQs.
- The official Motorola | 68HC11A8 Data Sheet. Fairly cryptic...
- A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
- Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
- Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
- The condition code register is covered in Section 3.5.
- M68HC11 Technical Reference, Motorola
- Section 6.5 shows the instructions in logical groups.
- M68HC11 Pocket Reference.
- Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
- 68HC11A8 Technical Reference: a hardware and engineering description. of the 6811, its ports, and how it operates.
- See Section 10 for a cycle-by-cycle description of the execution of each instruction.
- See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.
Back To Main Page
