Difference between revisions of "CSC270 Homework 11 2012"
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=Problem 1= | =Problem 1= | ||
| − | Use the Xilinx ISE to create a sequencer that is the answer of [[CSC270_Homework_5_2012 | Problem # | + | Use the Xilinx ISE to create a sequencer that is the answer of [[CSC270_Homework_5_2012 | Problem #1 of Homework 5]]. |
You must turn in: | You must turn in: | ||
* A screen copy of your schematics. | * A screen copy of your schematics. | ||
| − | * A copy of the Verilog | + | * A copy of the Verilog test program. |
* A screen copy of the timing diagram showing the correct behavior of your sequencer. | * A screen copy of the timing diagram showing the correct behavior of your sequencer. | ||
| + | =Problem 2= | ||
| + | |||
| + | Same as Problem 1, but this time your circuit will be the answer of [[CSC270_Homework_5_2012 | Problem #'''2''' of Homework 5]]. | ||
<br /> | <br /> | ||
Latest revision as of 09:04, 25 April 2012
--D. Thiebaut 10:02, 25 April 2012 (EDT)
This Homework on Wednesday 5/2/12, at 1:00 p.m. You can work on it in groups of at most 2 people if you want. You will have to use the Xilinx ISE, which is available on the CS Laptops in FH143. This software is not available anywhere else. You can install it on your own Windows (or Mac equipped with Parallels) if you wish. Instructions for the (complex) installation procedure are available here. The DVD with the ISE is available in an envelop, right next to my office door.
Problem 1
Use the Xilinx ISE to create a sequencer that is the answer of Problem #1 of Homework 5.
You must turn in:
- A screen copy of your schematics.
- A copy of the Verilog test program.
- A screen copy of the timing diagram showing the correct behavior of your sequencer.
Problem 2
Same as Problem 1, but this time your circuit will be the answer of Problem #2 of Homework 5.
