Difference between revisions of "DT's Research Page"
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<meta name="title" content="Dominique Thiebaut's Research Page" /> | <meta name="title" content="Dominique Thiebaut's Research Page" /> | ||
| + | <meta name="keywords" content="computer science, connex array, connex, connex memory, transputer, cache memories" /> | ||
| + | <meta name="description" content="Dominique Thiebaut's Web Page" /> | ||
| + | <meta name="title" content="Dominique Thiebaut -- Computer Science" /> | ||
| + | <meta name="abstract" content="Dominique Thiebaut's Computer Science Web pages" /> | ||
| + | <meta name="author" content="thiebaut at cs.smith.edu" /> | ||
| + | <meta name="distribution" content="Global" /> | ||
| + | <meta name="revisit-after" content="10 days" /> | ||
| + | <meta name="copyright" content="(c) D. Thiebaut 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,2008" /> | ||
| + | <meta name="robots" content="FOLLOW,INDEX" /> | ||
| + | |||
<!--div id="advert">[http://www.prchecker.info/ [[Image:PR1_img.gif|Display Pagerank]]]</div--> | <!--div id="advert">[http://www.prchecker.info/ [[Image:PR1_img.gif|Display Pagerank]]]</div--> | ||
= Industry = | = Industry = | ||
| − | D. Thiébaut is one of the five co-founders of Gemicer, which after changing its name to [http://www.connextechnology. | + | D. Thiébaut is one of the five co-founders of Gemicer, which after changing its name to [http://www.connextechnology.com/index.asp Connex Technology], has now adopted the current name of [http://www.brightscale.com BrightScale]. |
| − | |||
| − | D. Thiébaut is the holder with George Stefan of two patents, one of which (US Patent 6,760,821) the company is based. | + | D. Thiébaut is the holder with George Stefan of two patents, one of which (US Patent 6,760,821) the company is based on. |
| − | Connex Technology/BrightScale is a fab-less start-up company conceived in April 2002, and funded by Adams Capital | + | Connex Technology/BrightScale is a fab-less start-up company conceived in April 2002, and funded by Adams Capital Management ([http://www.acm.com www.acm.com]) in April 2003. |
| − | |||
| − | More information on the history of the Connex Engine can be found [http://arh.pub.ro/gstefan/conexMemory.html here]. | + | More information on the history of the Connex Engine can be found <!--[http://arh.pub.ro/gstefan/conexMemory.html here]-->[[ConnexProjectHistory | here]]. |
| + | |||
| + | D. Thiébaut holds a Ph.D. in Electrical and Computer Engineering from the University of Massachusetts, at Amherst, MA, USA. | ||
= Patents and Invention Disclosures = | = Patents and Invention Disclosures = | ||
| − | * [ | + | * [[media:UnitedStatePatent7069386.pdf | Associative Memory Device]], Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu, '''United States Patent''' 7,069,386, granted June 27, 2006. |
| − | * [ | + | * [[media:UnitedStatePatent6760821.pdf | Memory engine for the inspection and manipulation of data]], Gheorghe Stefan & Dominique Thiébaut, '''United States Patent''' 6,760,821, granted July 6, 2004 ([patent/USPatent6760821.htm cached]). Also issued as Patent #5227-0002WOKR (Korea). |
| − | * A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a cache of fixed size, Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''', Sept. 1990 | + | <!--* A scheme for producing miss-rate as a function of cache size by means of traces produced by observing misses from a cache of fixed size, Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''', Sept. 1990--> |
* A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, '''IBM Invention Disclosure''' YO889-0493, Jun. 1989. | * A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, '''IBM Invention Disclosure''' YO889-0493, Jun. 1989. | ||
* A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''' YO889-0515, Jun. 1989. | * A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, '''IBM Invention Disclosure''' YO889-0515, Jun. 1989. | ||
| + | <br /> | ||
| + | = Selected Papers = | ||
| + | |||
| + | ==Education== | ||
| + | * [[media:Thiebaut_automaticEvaluationOfComputerProgramsUsingMoodlesVirtualProgrammingLabModule3.pdf|Automatic Evaluation of Computer Programs using Moodle's Virtual Programming Lab (VPL) Module]], D. Thiebaut, accepted for presentation at CCSCNE 2015. | ||
| + | <br /> | ||
| + | |||
| + | ==Algorithms== | ||
| + | * [http://cs.smith.edu/dftwiki/images/2DpackingBillionThiebautPaperIaria_7028.pdf 2D Packing on a Large Scale: Packing a Billion Rectangles under 10 Minutes], D. Thiebaut, [http://www.iariajournals.org/systems_and_measurements/sysmea_v7_n12_2014_paged.pdf ''Int'l Journal in Advances in Systems and Measurements,''] vol. 7, no. 1&2, pp. 80-90, July 2014. | ||
| + | * [http://cs.smith.edu/dftwiki/images/PackingImagesOnALargeScale_Thiebaut_InfoComp2013.pdf 2D Packing on a Large Scale], D. Thiebaut, in ''Proceedings of INFOCOMP 2013'', Lisbon, Portugal, Nov. 2013. (<font color="#ff0000">Awarded best paper of InfoComp2013.</font>) | ||
| + | * [[Media:PushPushIsNPHard.pdf | PushPush is NP-hard in 3D]], J. O'Rourke, B. Chaudry, S. Chircu, E. F. Churchill, S. Fedorova, J. Franklin, B. Kaneva, H. Miller, A. Okmianski, I. Pashchenko, I. Streinu, G. Tewari, D Thiebaut, Elif Tosun, in ''Proceedings of CoRR'', 1999. | ||
| + | <br /> | ||
| + | |||
| + | ==Cloud Computing== | ||
| + | * [[Media:XGridHadoopCloser2011.pdf | Processing Wikipedia Dumps: A Case-Study comparing the XGrid and MapReduce Approaches]], D. Thiebaut, Yang Li, Diana Jaunzeikare, Alexandra Cheng, Ellysha Raelen Recto, Gillian Riggs, Xia Ting Zhao, Tonje Stolpestad, and Cam Le T Nguyen, ''in proceedings of 1st Int'l Conf. On Cloud Computing and Services Science'' (CLOSER 2011), Noordwijkerhout, NL, May 2011. ([[Media:XGridHadoopFeb2011.pdf |longer version]]) | ||
| + | <br /> | ||
| + | ==Digital Humanities== | ||
| + | * [[Media:Visnomad_IVAPP10.pdf | Encyclopedia Walkabouts with Visnomad: A New Visualization Tool Designed as an Aid for Textual Exploration]], D. Thiebaut and L. Owens, ''Int'l conference on Information Visualization Theory and Application'' (IVAPP), Angers, France, 2010. (See [http://visnomad.org Visnomad] Web site for more information) | ||
| − | = | + | * [[Report from Computerville: Virtual Walkabouts and Master Narratives]], L. Owens and D. Thiebaut, ''Massachusetts Review'', Spring 2011 issue. |
| + | <br /> | ||
| + | |||
| + | ==Data Visualization== | ||
| + | * [[Media:DataVisAgentBasedModelingVirusSpread_GanThiebaut2017.pdf |Data Visualization of Agent-Based Modeling of Virus Spread ]], J. Gan, and D. Thiebaut, ''INFOCOMP 2017'', June 25-29, 2017, Venice, Italy. | ||
| + | <!-- | ||
== Wikipedia == | == Wikipedia == | ||
| − | * [http://cs.smith.edu/~thiebaut/wikipedia/thiebaut_whatwewiki.pdf What We Wiki], D. Thiebaut, Technical Report, Smith College, July 2007. [in [http://cs.smith.edu/~thiebaut/wikipedia/quisontceswikipediens.txt French]] ( | + | * [http://cs.smith.edu/~thiebaut/wikipedia/thiebaut_whatwewiki.pdf What We Wiki], D. Thiebaut, Technical Report, Smith College, July 2007. [in [http://cs.smith.edu/~thiebaut/wikipedia/quisontceswikipediens.txt French]] ([[What_We_Wiki | Methodology]]) |
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| + | <br /> | ||
== Connex Memory, Connex Engine == | == Connex Memory, Connex Engine == | ||
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| + | <!-- | ||
== Teaching Computer Science == | == Teaching Computer Science == | ||
* [http://cs.smith.edu/~thiebaut/research/ccsne07/teachingArchitecture.pdf On Startups and Teaching Computer Architecture], D. Thiébaut, CCSCNE 07, Rochester, NY, Apr. 2007. | * [http://cs.smith.edu/~thiebaut/research/ccsne07/teachingArchitecture.pdf On Startups and Teaching Computer Architecture], D. Thiébaut, CCSCNE 07, Rochester, NY, Apr. 2007. | ||
| + | --> | ||
| + | <!-- | ||
== Performance measuring tool == | == Performance measuring tool == | ||
* [http://cs.smith.edu/~thiebaut/research/msr/msrpaper.pdf An MSR-based performance measuring tool for Intel Processors under Linux], [http://ozventures.hampshire.edu/~ealtieri/ E. Altieri], and D. Thiébaut, Tech. Rep. 075, Dept. Computer Science, Smith College, Dec. 2001. ([[msr source code]]) | * [http://cs.smith.edu/~thiebaut/research/msr/msrpaper.pdf An MSR-based performance measuring tool for Intel Processors under Linux], [http://ozventures.hampshire.edu/~ealtieri/ E. Altieri], and D. Thiébaut, Tech. Rep. 075, Dept. Computer Science, Smith College, Dec. 2001. ([[msr source code]]) | ||
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== Parallel Programming with Transputers == | == Parallel Programming with Transputers == | ||
* [http://cs.smith.edu/~thiebaut/transputer/descript.html Parallel Programming in C for the Transputer], D. Thiébaut | * [http://cs.smith.edu/~thiebaut/transputer/descript.html Parallel Programming in C for the Transputer], D. Thiébaut | ||
| − | * Randomized Routing for Message Passing Using Virtual Channels: Mitra, S, and D. Thiébaut, The Inebriated Router Algorithm, in '' proc. 1993 North American Transputer User Group Meeting'' Vancouver, B.C., Canada | + | * Randomized Routing for Message Passing Using Virtual Channels: Mitra, S, and D. Thiébaut, The Inebriated Router Algorithm, in '' proc. 1993 North American Transputer User Group Meeting'' Vancouver, B.C., Canada |
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| + | <br /> | ||
== Cache Memories and Coherence Protocols == | == Cache Memories and Coherence Protocols == | ||
| Line 60: | Line 102: | ||
* Improving disk cache performance with partitioning, Thiébaut, D., H. S. Stone, and J. L. Wolf, ''IEEE Transactions on Computers'' | * Improving disk cache performance with partitioning, Thiébaut, D., H. S. Stone, and J. L. Wolf, ''IEEE Transactions on Computers'' | ||
* Synthetic traces for trace-driven simulation of cache memories, Theibaut, D., J. L. Wolf, and H. S. Stone, ''IEEE Trans. Computers'' | * Synthetic traces for trace-driven simulation of cache memories, Theibaut, D., J. L. Wolf, and H. S. Stone, ''IEEE Trans. Computers'' | ||
| − | * A Model of | + | * A Model of workloads and its ue in miss-rate prediction for fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, ''IEEE Transactions on Computers'' |
* fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, ''IEEE Transactions on Computers'' | * fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, ''IEEE Transactions on Computers'' | ||
* Modeling live and dead lines in cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, ''IEEE Transactions on Computers'' | * Modeling live and dead lines in cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, ''IEEE Transactions on Computers'' | ||
| Line 68: | Line 110: | ||
* A hierarchical directory scheme for large-scale cache-coherent multiprocessors, Maa, Y. C., D. K. Pradhan, and D. Thiébaut, 1992 Int'l Parallel Processing Symposium | * A hierarchical directory scheme for large-scale cache-coherent multiprocessors, Maa, Y. C., D. K. Pradhan, and D. Thiébaut, 1992 Int'l Parallel Processing Symposium | ||
| + | <!-- | ||
== Chaos and nonlinear dynamics == | == Chaos and nonlinear dynamics == | ||
* [http://cs.smith.edu/~thiebaut/research/splining.pdf Smoothing Stange Attractors with Splines], Junheng Luo and D. Thiébaut, Tech. Rep. 045, Dept. Computer Science, Smith College. ([ftp://cs.smith.edu/pub/thiebaut/chaos postscript]) | * [http://cs.smith.edu/~thiebaut/research/splining.pdf Smoothing Stange Attractors with Splines], Junheng Luo and D. Thiébaut, Tech. Rep. 045, Dept. Computer Science, Smith College. ([ftp://cs.smith.edu/pub/thiebaut/chaos postscript]) | ||
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Latest revision as of 14:26, 26 September 2017
<meta name="title" content="Dominique Thiebaut's Research Page" /> <meta name="keywords" content="computer science, connex array, connex, connex memory, transputer, cache memories" /> <meta name="description" content="Dominique Thiebaut's Web Page" /> <meta name="title" content="Dominique Thiebaut -- Computer Science" /> <meta name="abstract" content="Dominique Thiebaut's Computer Science Web pages" /> <meta name="author" content="thiebaut at cs.smith.edu" /> <meta name="distribution" content="Global" /> <meta name="revisit-after" content="10 days" /> <meta name="copyright" content="(c) D. Thiebaut 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,2008" /> <meta name="robots" content="FOLLOW,INDEX" />
Industry
D. Thiébaut is one of the five co-founders of Gemicer, which after changing its name to Connex Technology, has now adopted the current name of BrightScale.
D. Thiébaut is the holder with George Stefan of two patents, one of which (US Patent 6,760,821) the company is based on. Connex Technology/BrightScale is a fab-less start-up company conceived in April 2002, and funded by Adams Capital Management (www.acm.com) in April 2003.
More information on the history of the Connex Engine can be found here.
D. Thiébaut holds a Ph.D. in Electrical and Computer Engineering from the University of Massachusetts, at Amherst, MA, USA.
Patents and Invention Disclosures
- Associative Memory Device, Gheorghe Stefan, Dominique Thiebaut, Dan Tomescu, United States Patent 7,069,386, granted June 27, 2006.
- Memory engine for the inspection and manipulation of data, Gheorghe Stefan & Dominique Thiébaut, United States Patent 6,760,821, granted July 6, 2004 ([patent/USPatent6760821.htm cached]). Also issued as Patent #5227-0002WOKR (Korea).
- A means for controlling the cache allocation of multiple disks in a shared disk cache, Joel Wolf, Harold Stone, and D. Thiébaut, IBM Invention Disclosure YO889-0493, Jun. 1989.
- A means for limiting the cache-reload transient caused by interrupt programs. Harold Stone, and D. Thiebaut, IBM Invention Disclosure YO889-0515, Jun. 1989.
Selected Papers
Education
- Automatic Evaluation of Computer Programs using Moodle's Virtual Programming Lab (VPL) Module, D. Thiebaut, accepted for presentation at CCSCNE 2015.
Algorithms
- 2D Packing on a Large Scale: Packing a Billion Rectangles under 10 Minutes, D. Thiebaut, Int'l Journal in Advances in Systems and Measurements, vol. 7, no. 1&2, pp. 80-90, July 2014.
- 2D Packing on a Large Scale, D. Thiebaut, in Proceedings of INFOCOMP 2013, Lisbon, Portugal, Nov. 2013. (Awarded best paper of InfoComp2013.)
- PushPush is NP-hard in 3D, J. O'Rourke, B. Chaudry, S. Chircu, E. F. Churchill, S. Fedorova, J. Franklin, B. Kaneva, H. Miller, A. Okmianski, I. Pashchenko, I. Streinu, G. Tewari, D Thiebaut, Elif Tosun, in Proceedings of CoRR, 1999.
Cloud Computing
- Processing Wikipedia Dumps: A Case-Study comparing the XGrid and MapReduce Approaches, D. Thiebaut, Yang Li, Diana Jaunzeikare, Alexandra Cheng, Ellysha Raelen Recto, Gillian Riggs, Xia Ting Zhao, Tonje Stolpestad, and Cam Le T Nguyen, in proceedings of 1st Int'l Conf. On Cloud Computing and Services Science (CLOSER 2011), Noordwijkerhout, NL, May 2011. (longer version)
Digital Humanities
- Encyclopedia Walkabouts with Visnomad: A New Visualization Tool Designed as an Aid for Textual Exploration, D. Thiebaut and L. Owens, Int'l conference on Information Visualization Theory and Application (IVAPP), Angers, France, 2010. (See Visnomad Web site for more information)
- Report from Computerville: Virtual Walkabouts and Master Narratives, L. Owens and D. Thiebaut, Massachusetts Review, Spring 2011 issue.
Data Visualization
- Data Visualization of Agent-Based Modeling of Virus Spread , J. Gan, and D. Thiebaut, INFOCOMP 2017, June 25-29, 2017, Venice, Italy.
Connex Memory, Connex Engine
- Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation, M. Malita, G. Stefan, D. Thiebaut, in ACM Sigarch Computer Architecture News, Vol. 35, No. 5, Dec. 2007.
- Not Multi-, but Many-Core: Designing Integral Parallel Architectures for Embedded Computation, G. Stefan, M. Malita, D. Thiebaut, in proceedings of ALPS, the 21st ACM International Conference on Supercomputing, Seattle, WA, June 2007.
- Pipelining the Connex Array, D. Thiébaut, M. Malita, BARC07, Boston, Jan. 2007.
- Local Alignment of DNA Sequences with the Connex Array, D. Thiébaut, G. Stefan, M. Malita, Int'l Conf. on Comp. in Global Information. Tech. (ICCGI06), Bucharest, Romania, Aug. 2006. (Awarded best paper of ICCGI06).
- Real-time Packet Filtering with the Connex Array, D. Thiébaut, M. Malita, Anchor/Isca06, Boston June 2006.
- Ziv-Lempel Compression with the Connex Engine, D. Thiébaut and G. Stefan, Tech Rep. 077, Dept. Computer Science, Smith College, Jan 2002. (postscript)
- Local Alignments of DNA Sequences with the Connex Engine, D. Thiébaut and G. Stefan, Tech Rep. 076, Dept. Computer Science, Smith College.
Parallel Programming with Transputers
- Parallel Programming in C for the Transputer, D. Thiébaut
- Randomized Routing for Message Passing Using Virtual Channels: Mitra, S, and D. Thiébaut, The Inebriated Router Algorithm, in proc. 1993 North American Transputer User Group Meeting Vancouver, B.C., Canada
Cache Memories and Coherence Protocols
- Footprints in the cache, D. Thiébaut and H. Stone, ACM Trans. on Comp. Syst.
- From the fractal dimension of the intermiss gaps to the cache miss-ratio, D. Thiébaut, IBM Journal of Research and Development
- On the fractal dimension of computer programs and its application to the computation of the cache miss-ratio, D. Thiébaut, IEEE Transactions on Computers
- Two economical directory schemes for large-scale cache coherent multiprocessors, Maa, Y. C., D. Pradhan, and D. Thiébaut, Computer Architecture News
- Improving disk cache performance with partitioning, Thiébaut, D., H. S. Stone, and J. L. Wolf, IEEE Transactions on Computers
- Synthetic traces for trace-driven simulation of cache memories, Theibaut, D., J. L. Wolf, and H. S. Stone, IEEE Trans. Computers
- A Model of workloads and its ue in miss-rate prediction for fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, IEEE Transactions on Computers
- fully associative caches, Singh, J. P., H. S. Stone, and D. Thiébaut, IEEE Transactions on Computers
- Modeling live and dead lines in cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, IEEE Transactions on Computers
- The hierarchical full-map directory scheme: Protocol and performance, Maa, Y. C., D. Pradhan, and D. Thiébaut, IEEE Transactions on Computers
- On the fractal dimension of computer programs and its application to the prediction of the cache miss ratio, D. Thiébaut, Computer Measurement Group Trans.
- Modeling of live lines and true sharing in multi-cache memory systems, Mendlson, A., D. Thiébaut, and D. Pradhan, in Proc. of the 1990 Int'l Conf. on Parallel Processing
- A hierarchical directory scheme for large-scale cache-coherent multiprocessors, Maa, Y. C., D. K. Pradhan, and D. Thiébaut, 1992 Int'l Parallel Processing Symposium
