Difference between revisions of "CSC270 Class Page 2011"

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(Weekly Schedule)
(Weekly Schedule)
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** lab
 
** lab
 
* '''Wednesday'''
 
* '''Wednesday'''
* '''Friday'''
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* '''Friday''': No Class
 
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Revision as of 14:30, 17 January 2011

--D. Thiebaut 08:44, 7 January 2011 (EST)




Back to Main Page for CSC270



Prof

Dominique Thiébaut email
Dept. Computer Science
Ford Hall, 356.
Telephone: 3854
Office hours TBA, and by appointments


Weekly Schedule


This section is only visible to computers located at Smith College


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Links and Resources

Programs

Software

Pspice9.jpg

PSpice 9

  • Pspice 9, Student version. An nice alternative to drawing schematics by hand.
  • This is a Windows version. (I have tried to make it work under wine/Mac OS X but haven't been able to make it load the libraries correctly)
  • Make sure you select the schematics option when installing the software.
  • Select Tools/Schematics when starting the editor
  • The schematics editor is located in C:\Program Files\OrCAD_Demo\PSpice\PDesign.exe upon installation.
  • Download here!
  • PSpice Tutorial

Integrated Circuit Data-Sheets

Ic.jpg

Motorola 68HC11 Documentation

6811.jpg
  • Good source of info on the 6811.
  • 6811 FAQs.
  • The official Motorola | 68HC11A8 Data Sheet. Fairly cryptic...
  • A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
    • Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
    • Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
    • The condition code register is covered in Section 3.5.
  • M68HC11 Technical Reference, Motorola
    • Section 6.5 shows the instructions in logical groups.
  • M68HC11 Pocket Reference.
    • Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
  • 68HC11A8 Technical Reference: a hardware and engineering description. of the 6811, its ports, and how it operates.
    • See Section 10 for a cycle-by-cycle description of the execution of each instruction.
    • See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.





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