CSC270 Weekly Schedule 2012

--D. Thiebaut 15:03, 18 January 2012 (EST)

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Main Page | Weekly Schedule

Office Hours: M 1:10-3:00 p.m., W 4:00-6:00 p.m.

Weekly Schedule

First Half

Week	Topics	Reading
Week  1 1/27	Friday Introduction Syllabus Digital circuits Mini-Lab: just to get the idea!	Skip Chapter 1.
Week 2 1/30	Monday Boolean Algebra Truth tables Venn diagrams examples of schematics from Nasa logic gates and gate (7408) or gate (7432) not gate (7404) Wednesday Boolean functions canonical forms: the minterm canonical form Friday Exercises on the duality of Boolean Logic Translating Schematics into a boolean function. Verifying truth tables in Python Mystery Circuit: Lab #1 Homework #1	Start your reading with Chapter 2 on Boolean Algebra. Binary numbers Boolean algebra and Logic Gates Basic theorems Truth tables Boolean functions Canonical forms George Boole
Week 3 2/6	Monday Maxterm Canonical Form Nand/Nor circuits Wednesday Rules of simplification and lazy evaluation by compilers... Karnaugh Maps The Decoder Exercises on Karnaugh maps, nands, and majority voters Don't Care conditions in Karnaugh Maps Friday Lab #2 Homework #2 and Solutions	Reading Karnaugh Maps Decoders
Week 4 2/13	Monday (Image from Eniac image Clemson U.) Comments on transistors and gates Equivalent of a Decoder in Java or Python? Karnaugh maps for 3, 4, and 5 variables. Don't care conditions with Karnaugh maps Wednesday Exercises Decoders with an enable input. (moving toward microprocessor architecture) Friday Decoders and Multiplexers in Computers IBM PC Schematics (circa 1984): spot the decoders! RAM Lab #3 Homework #3 and solutions	Chapter 4: decoders, multiplexers
Week 5 2/20	Monday Something to study for a while... Answer of the day: It's a sequential circuit: it behaves differently depending on initial conditions! It's a machine with 2 states: it has a state diagram! We cannot use a truth table to represent its behavior It has memory: it can store a bit Why does it work? Because the two gates that form this circuit can be eith blocking or passing, and when they are passing, the state, whichever it is, is stable. End of the lecture was with timing diagrams, and showing that Q and Q' can be in either one of the possible cases: 01 or 10, and we show that on the timing diagram. Wednesday Toward the D Flip-Flop: From RS to RS with 1 input only From RS with 1 input only to RS with a pulse clock latch signal From RS with a latch signal to a Master/Slave (sorry, this is the way it is coined) flip-flop The D Flip-Flop. 74LS74 datasheet. Friday Comments on last lab: A note on scale: http://htwins.net/scale2/ units are important! Know the difference between Volts, millivolts, seconds, milliseconds, microseconds, nanoseconds. How does a scope work? Synchronizing waveforms Grounding Exercises Lab #4 Homework #4 and solution	Chapter 5: synchronous sequential logic
Week 6 2/27	Monday Finite State Machines: Moore vs. Mealy machines. Two examples: a two-state oscillator, and a controlled oscillator Designing a FSM that has a command input. If the command signal (cmd) is 1, the FSM oscillates. If the command signal is 0, the FSM stays in its current state. Draw the state diagram Figure out the number of flip-flops needed Draw the State table, associating States to values of the Q output(s) Draw the State Transition table. Define the D inputs as a function of the Q outputs Draw the FSM with flip-flop(s) and combinational logic Verify with a timing diagram that the circuit works Wednesday Review of multiplexers and decoders as simplifying design blocks Exercises on FSMs A Python program to simulate a sequencer. Preparation for Lab #5: design the circuit for the last problem Friday Python Logic Operators Example Page Exercises on FSMs Lab #5 Homework #5 and Solution	Chapter 5: synchronous sequential logic
Week 7 3/5	Monday The JK Flip-Flop diagram Exercise 1: Let's figure out how to design a FSM without external input first. Exercise 2: Same idea, with a user input. Wednesday Exercises with the JK Flip-Flop Friday Midterm Prep Lab #6 Homework #6
Week 8 3/12	Monday ROM-Based Sequencers (Good reference) Introduction to the 6811. Wednesday : Midterm Exam Introduction to the 6811 Friday R&R Lab 7 (mini lab at the end of introduction to 6811).
Week 9 3/19	SPRING BREAK

Second Half

Week	Topics	Reading
Week  1 3/26	Monday Review of 6811 Mini Lab (at end of Intro to 6811) Comments on past Midterm Wednesday Friday	Reading: A good tutorial on 6811 assembly language (pdf) Feel free to also sample the information in the References section of the Introduction to the 6800 we saw in class.
Week 10 4/02	Monday Wednesday Friday
Week 11 4/09	Monday Wednesday Friday
Week 12 4/16	Monday Wednesday Friday
Week 13 4/23	Monday Wednesday Friday
Week 14 4/30	Monday Wednesday: Last Day of Class

Links and Resources

Printing

• How to print a text file (pure ASCII, not an MS Word document) from a beowulf account to the printer @ FH354:

  cprint -15  myFile.txt

• How to print a pdf from a beowulf account to the printer @ FH354:

  lpr -P ford354 max232.pdf

• How to print an image to the same printer, from a beowulf account:

  convert myImage.jpg  myImage.pdf
  lpr -P ford354 myImage.pdf

Programs

• How to implement AND, OR, NOT and simple logic circuits in Python
• A Python program that generates a truth table.
• A Python program to simulate a simple sequencer.

Software

Demos of Various Circuit

• Hades at U. of Hamburg.

Free Circuit CAD Systems

• CircuitLab

(the video shows an analog circuit, but logic gates are also supported)

• TinyCAD

• http://www.xmarks.com/site/www.tech-systems-labs.com/freesoftware.htm

PSpice 9

• Pspice 9, Student version. An nice alternative to drawing schematics by hand.
• This is a Windows version. (I have tried to make it work under wine/Mac OS X but haven't been able to make it load the libraries correctly)
• Make sure you select the schematics option when installing the software.
• Select Tools/Schematics when starting the editor
• The schematics editor is located in C:\Program Files\OrCAD_Demo\PSpice\PDesign.exe upon installation.
• Download here!
• PSpice Tutorial

Integrated Circuit Data-Sheets

• Java Applets demonstrating most logical gates
• Texas Instruments and Harris Semiconductors' Data Sheet Search Engine
• Fairchild Semiconductors' Data Sheet Search Engine
• 74LS00, 74LS01, 74LS02, 74LS03, 74LS04, 74LS05, 74LS08, 74LS09, 74LS10, 74LS12, 74LS13, 74LS15, 74LS20, 74LS21, 74LS22, 74LS26, 74LS27, 74LS28, 74LS30, 74LS32, 74LS33, 74LS37, 74LS38, 74LS40, 74LS42, 74LS47, 74LS48, 74LS51, 74LS54, 74LS55, 74LS74, 74LS75, 74LS76, 74LS83, 74LS85, 74LS86, 74LS90, 74LS95, 74LS138, 74HCT240, 74LS243, 74HCT244, 74LS259, 74HCT541

• 9368
• 2114 1Kx4 RAM ( with timing information )
• Octal D-Flipflop (we do not have these chips in our current collection of chips)

Motorola 68HC11 Documentation

• A good tutorial on 6811 assembly language (pdf)
• 6811 FAQs.
• The official Motorola 68HC11A8 Data Sheet. Fairly cryptic...
• A Motorola 6811 Manual. It is a nicely written refresher on many concepts of assembly language applied to the 6811.
  • Check Section 3.2 on addressing modes (inherent, direct, extended, indexed, relative).
  • Get a refresher for the different instruction types (arithmetic, shifts, control, etc) in Section 3.4.
  • The condition code register is covered in Section 3.5.
• M68HC11 Technical Reference, Motorola
  • Section 6.5 shows the instructions in logical groups.
• M68HC11 Pocket Reference.
  • Very useful, on Page 15, a list of all the opcodes supported by the 6811, in numerical (hex) order.
• 68HC11A8 Technical Reference: a hardware and engineering description. of the 6811, its ports, and how it operates.
  • See Section 10 for a cycle-by-cycle description of the execution of each instruction.
  • See Appendix A, Figure A-14 for the timing diagram of a typical (multiplexed expansion) memory access.
• Heathkit ETW3800 Trainer manual (pdf)
• Input/Output with the 6811: Memory-Mapped I/O (Heathkit documentation)

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